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19-2229; Rev 0; 10/01
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
General Description
The MAX1407/MAX1408/MAX1409/MAX1414 are lowpower, general-purpose, multichannel data-acquisition systems (DAS). These devices are optimized for lowpower applications. All the devices operate from a single +2.7V to +3.6V power supply and consume a maximum of 1.15mA in Run mode and only 2.5A in Sleep mode. The MAX1407/MAX1408/MAX1414 feature a differential 8:1 input multiplexer to the ADC, a programmable three-state digital output, an output to shutdown an external power supply, and a data ready output from the ADC. The MAX1408 has eight auxiliary analog inputs, while the MAX1407/MAX1414 include four auxiliary analog inputs and two 10-bit force/sense DACs. The MAX1414 features a 50mV trip threshold for the signal-detect comparator while the others have a 0mV trip threshold. The MAX1409 is a 20-pin version of the DAS family with a differential 4:1 input multiplexer to the ADC, one auxiliary analog input, and one 10-bit force/sense DAC. The MAX1407/MAX1408/MAX1414 are available in space-saving 28-pin SSOP packages, while the MAX1409 is available in a 20-pin SSOP package.
Features
o +2.7V to +3.6V Supply Voltage Range in Standby, Idle, and Run Mode (Down to 1.8V in Sleep Mode) o 1.15mA Run Mode Supply Current o 2.5A Sleep Mode Supply Current (Wake-Up, RTC, and Voltage Monitor Active) o Multichannel 16-Bit Sigma-Delta ADC 1.5 LSB (typ) Integral Nonlinearity 30Hz or 60Hz Continuous Conversion Rate Buffered or Unbuffered Mode Gain of +1/3, +1, or +2V/V Unipolar or Bipolar Mode On-Chip Offset Calibration o 10-Bit Force/Sense DACs o Buffered 1.25V, 18ppm/C (typ) Bandgap Reference Output o SPITM/QSPITM or MICROWIRETM-Compatible Serial Interface o System Support Functions RTC (Valid til 9999) and Alarm High-Frequency PLL Clock Output (2.4576MHz) +1.8V and +2.7V RESET and Power-Supply Voltage Monitors Signal Detect Comparator Interrupt Generator (INT and DRDY) Three-State Digital Output Wake-Up Circuitry o 28-Pin SSOP (MAX1407/MAX1408/MAX1414), 20-Pin SSOP (MAX1409)
MAX1407/MAX1408/MAX1409/MAX1414
Applications
Medical Instruments Industrial Control Systems Portable Equipment Data-Acquisition System Automatic Testing Robotics
Pin Configurations
TOP VIEW
FB2 1 DO 2 FB1 3 OUT1 4 IN0 5 REF 6 AGND 7 AVDD 8 CPLL 9 WU1 10 WU2 11 RESET 12 IN1 13 IN2 14 28 OUT2 27 IN3 26 DVDD 25 DGND 24 CS 23 SCLK
Ordering Information
PART MAX1407CAI MAX1408CAI MAX1409CAP MAX1414CAI TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 28 SSOP 28 SSOP 20 SSOP 28 SSOP
MAX1407 MAX1414
22 DIN 21 DOUT 20 INT 19 CLKIN 18 CLKOUT 17 FOUT 16 DRDY 15 SHDN
Pin Configurations continued at end of data sheet. Typical Operating Circuit appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V AVDD to DVDD ...................................................... -0.3V to +0.3V Analog Inputs to AGND .........................-0.3V to +(AVDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V Maximum Current Input Into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin SSOP (derate 8.0mW/C above +70C) ...........640mW 28-Pin SSOP (derate 9.52mW/C above +70C) .........762mW DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Analog Outputs to AGND ......................-0.3V to +(AVDD + 0.3V) Digital Outputs to DGND .......................-0.3V to +(AVDD + 0.3V) REF to AGND.........................................-0.3V to +(AVDD + 0.3V) Operating Temperature Range: MAX14__CA_ ......................................................0C to +70C MAX14__EA_ ...................................................-40C to +85C Lead Temperature (soldering, 10s) ................................+300 C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD = AVDD = +2.7V to 3.6V, 4.7F at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and CLKOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ADC ACCURACY Resolution (No Missing Codes) RES Unbuffered mode, Unipolar mode, gain = 1, VNEG = 0.2V, fully differential input (Note 7) Unbuffered mode, Unipolar mode, gain = 2, VNEG = 0.625V, pseudo-differential input Unbuffered mode, Bipolar mode, gain = 1, VNEG = 0.625V, fully differential input Buffered mode, Bipolar mode, gain = 2, VNEG = 0.625V, fully differential input Gain = 2 Unipolar Output RMS Noise (Note 1) Bipolar Mode Offset Error Offset Drift Gain Error Gain Drift Excludes offset and reference errors Excludes offset and reference errors 1 Gain = 1 Gain = 1/3 Gain = 2 Gain = 1 Gain = 1/3 On-chip calibration removes this error 0.5 1 16 1.5 1.75 LSB 1.70 2.50 5 10 30 8 16.5 48.5 1 % of FSR V/C % of FSR ppm/C VRMS 3.5 Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Nonlinearity
INL
2
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = AVDD = +2.7V to 3.6V, 4.7F at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and CLKOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PGA Gain Power-Supply Rejection Ratio Output Update Rate Turn-On Time SIGNAL DETECT COMPARATOR Differential Input-Detection Threshold Voltage Common-Mode Input Voltage Turn-On Time ANALOG INPUTS ADC gain = 1 Unipolar mode Differential Input Voltage Range Bipolar mode Unbuffered Buffered Unbuffered Buffered Gain = 1, unipolar and buffered mode FOUT = 2.4576MHz Buffered mode 30Hz data rate 60Hz data rate ADC gain = 2 ADC gain = 1/3 ADC gain = 1 ADC gain = 2 ADC gain = 1/3 Absolute Input Voltage Range Common-Mode Input Voltage Range Common-Mode Rejection Ratio Input Sampling Rate Input Current Input Capacitance FORCE-SENSE DAC (all measurements made with FB1(2) shorted to OUT1(2), unless otherwise noted). (MAX1407/MAX1409/MAX1414 only) Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Offset Drift Gain Error Gain Drift Line Regulation Current into FB1(2) Excludes offset and reference drift Excludes offset and reference drift 10 190 0.5 Guaranteed monotonic (Note 2) (Note 2) (Note 3) 5 3.6 10 1.0 1.0 20 Bits LSB LSB mV V/C mV ppm/C V/V nA 0 0 0 -VREF -VREF/2 -AVDD -0.05 0.05 AGND 0.05 90 15.360 30.720 0.5 15 VREF VREF/2 AVDD VREF VREF/2 AVDD AVDD 1.40 AVDD 1.40 V V dB kHz nA pF V MAX1407/MAX1408/MAX1409 MAX1414 -10 44 0 10 0 50 10 56 0.8 mV V s SYMBOL CONDITIONS See PGA Gain section Gain = 1, unipolar and buffered mode Continuous conversion Excluding reference RATE bit = 0 RATE bit = 1 MIN TYP 1/3 1 2 70 30 60 50 dB Hz s V/V MAX UNITS
MAX1407/MAX1408/MAX1409/MAX1414
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = AVDD = +2.7V to 3.6V, 4.7F at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and CLKOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output Slew Rate SYMBOL CONDITIONS 010hex to 3FFhex and 3FFhex to 010hex code swing, RL = 12k, CL = 200pF To 1/2 LSB (at 10-bit accuracy) of fullscale with code transition from 010hex to 3FFhex, RL = 12k, CL = 200pF MIN TYP 18.0 MAX UNITS V/ms
Output Settling Time Turn-On Time OUT1, OUT2 Output Range
65 100
s s AVDD - 0.2 V
No Load (Note 4)
0.05
EXTERNAL REFERENCE (internal reference powered down) Input Voltage Range Input Resistance Input Current INTERNAL REFERENCE (AVDD = 3V, unless otherwise noted) Output Voltage Output Voltage Temperature Coefficient Output Short-Circuit Current Line Regulation Load Regulation Noise Voltage Power-Supply Rejection Ratio Turn-On Time P RESET Supply Voltage Range RESET Trip Threshold Low Low AVDD Trip Threshold RESET Output Low Voltage (Open-Drain Output) VTH For valid RESET AVDD falling Bit VM = 1 Bit VM = 0 1 1.800 2.70 2.70 1.865 2.75 2.75 3.6 1.930 2.80 2.80 0.4 V V V V eOUT VREF/VDD TA = +25C 1.225 1.25 18 3.4 2.7For Normal, Idle, and Standby modes, AVDD falling ISINK = 1mA, AVDD = 1.8V
4
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = AVDD = +2.7V to 3.6V, 4.7F at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and CLKOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER RESET Output Leakage Turn-On Time CRYSTAL OSCILLATOR Crystal Frequency Crystal Load Capacitance Oscillator Stability Oscillator Startup Time PLL FOUT Frequency Absolute Clock Jitter Frequency Tolerance/Stability FOUT Rise/Fall Time Duty Cycle DIGITAL INPUTS (DIN, SCLK, CS, WU1, WU2) Input High Voltage Input Low Voltage Input Hysteresis DIN, SCLK, CS, Input Current WU1, WU2 Input Current WU1, WU2 Pullup Current Input Capacitance DIGITAL OUTPUTS (DOUT, FOUT, INT, DRDY, SHDN, D0) DOUT, FOUT, DRDY, INT Output Low Voltage DOUT, FOUT, DRDY, INT, SHDN Output High Voltage DOUT Three-State Leakage DOUT Three-State Capacitance SHDN Output Low Voltage (MAX1407/MAX1408/MAX1414 only) ISINK = 1mA, DVDD = +1.8V to +3.6V ISINK = 50A, DVDD = +1.8V to +3.6V VOL VOH ISINK = 1mA, DVDD = +1.8V to +3.6V ISOURCE = 0.2mA, DVDD = +1.8V to +3.6V 0.8 x DVDD 0.01 15 0.4 0.04 x DVDD V 10 0.4 V V A pF DVDD = +1.8V to +3.6V DVDD = +1.8V to +3.6V DVDD = +3V VIN = 0 or VIN = DVDD VIN = AVDD VIN = 0 200 0.01 0.01 10 10 10 10 0.7 x DVDD 0.3 x DVDD V V mV A A A pF AVDD = +3V Cycle-to-cycle Overtemperature excluding crystal, TA = TMIN to TMAX Oversupply voltage, +2.7V< AVDD< +3.6V 20% to 80% waveform, CL = 30pF 40 2.4576 10 0 0 15 50 30 60 MHz ns ppm/C ppm/mV ns % AVDD = +1.8V to +3.6V, excluding crystal AVDD = +3V 32.768 6 0 1.5 kHz pF ppm/V s SYMBOL CONDITIONS AVDD > VTH, RESET deasserted MIN TYP 0.002 2 MAX 0.1 UNITS A ms
MAX1407/MAX1408/MAX1409/MAX1414
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = AVDD = +2.7V to 3.6V, 4.7F at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and CLKOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER D0 Output Low Voltage (MAX1407/MAX1408/MAX1414 only) D0 Output High Voltage (MAX1407/MAX1408/MAX1414 only) POWER REQUIREMENTS Supply Voltage Range VDD Run, Idle, and Standby mode Sleep mode MAX1407/MAX1414 Run mode MAX1408 MAX1409 MAX1407/MAX1414 Supply Current (Note 5) IDD Idle mode MAX1408 MAX1409 Standby mode Sleep mode VDD = 2.7V MAX1407/MAX1408/ MAX1409/MAX1414 MAX1407/MAX1408/ MAX1409/MAX1414 1.7 2.7 1.8 3.6 3.6 1.15 1.03 1.09 650 530 590 330 2.5 A mA V SYMBOL CONDITIONS ISINK = 200A, DVDD = +2.7V to +3.6V MIN TYP MAX 0.7 UNITS mV
ISOURCE = 2mA, DVDD = +2.7V to +3.6V
DVDD - 0.1
V
TIMING CHARACTERISTICS
(MAX1407/MAX1408/MAX1409/MAX1414: AVDD = DVDD = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER TIMING PARAMETERS SCLK Operating Frequency SCLK Cycle Time SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold fSCLK tCYC tCH tCL tDS tDH tDO tDV tTR tCSS tCSH CL = 50pF (see load circuit) CL = 50pF (see load circuit) CL = 50pF (see load circuit) 100 0 476 190 190 100 0 200 240 240 2.1 MHz ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
6
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AVDD = DVDD = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER TYPICAL TIMING PARAMETERS OUT1/OUT2 Turn-Off Time Input impedance > 1M (MAX1407/MAX1409/MAX1414 only) The delay for the sleep voltage monitor output, RESET, to go high after AVDD rises above the reset threshold (+1.8V when bit VM = 1 and +2.7V, when bit VM = 0); this is largely driven by the startup of the 32kHz oscillator Minimum pulse width required to detect a wake-up event The delay for SHDN to go high after a valid wake-up event The turn-on time for the high-frequency clock; it is gated by an AND function with three signals--the RESET signal, the internal low voltage VDD monitor signal, and the assertion of the PLL; the time delay is timed from when the low-voltage monitor trips or the RESET going high, whichever happens later; FOUT always starts in the low state The delay for INT to go low after the FOUT clock output has been enabled; INT is used as an interrupt signal to inform the P the high-frequency clock has started The delay after a shutdown command has asserted and before FOUT is disabled; this gives the microcontroller time to clean up and go into Sleep mode properly The delay after a shutdown command has asserted and before SHDN is pulled low (turning off the DC-DC converter) (Note 6) 100 s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1407/MAX1408/MAX1409/MAX1414
Sleep Voltage Monitor Timeout Period
tDSLP
1.54
s
WU1 or WU2 Pulse Width Shutdown Deassert Delay
tWU tDPU
1 1
s s
FOUT Turn-On Time
tDFON
31.25
ms
INT Delay
tDFI
7.82
ms
FOUT Disable Delay
tDFOF
1.95
ms
SHDN Assertion Delay
tDPD
2.93
ms
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Single conversion. DNL and INL are measured between code 010hex and 3FFhex. Offset error is referenced to code 010hex. Output swing is a function of external gain-setting feedback resistors and REF voltage. Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DVDD. SHDN stays high if the PLL is on. Actual worst-case performance is 2.5LSB. Guaranteed limit of 3.5LSB is due to production test limitation. Guaranteed by design. Not production tested.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Load Circuits
DVDD 6k DOUT DOUT 6k DGND a) VOH TO HIGH-Z CLOAD 50pF CLOAD 50pF DGND b) VOL TO HIGH-Z 6k DGND a) HIGH-Z TO VOH AND VOL TO VOH CLOAD 50pF DOUT DOUT CLOAD 50pF DGND b) HIGH-Z TO VOL AND VOH TO VOL DVDD 6k
LOAD CIRCUITS FOR DISABLE TIME
LOAD CIRCUITS FOR ENABLE TIME
Typical Operating Characteristics
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1407 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX1407 toc02
700 600 RUN MODE SUPPLY CURRENT (A) 500 400 300 200 100 0 2.70 2.85 3.00 3.15 3.30 3.45 STANDBY IDLE MODE
700 600 RUN MODE SUPPLY CURRENT (A) 500 400 300 200 100 0 STANDBY IDLE MODE
3.60
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SLEEP CURRENT vs. FALLING VDD
MAX1407 toc03
SLEEP MODE SUPPLY CURRENT vs. TEMPERATURE
MAX1407 toc04
4.0 3.5 SLEEP CURRENT (A) 3.0 2.5 2.0 1.5 1.0 1.80 2.30 2.80 3.30 SUPLLY VOLTAGE (V)
3.0 2.5 SUPPLY CURRENT (A) 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60
85
TEMPERATURE (C)
8
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
MAXIMUM INL vs. VDD (UNIPOLAR MODE, T = +25C, PSEUDO-DIFFERENTIAL INPUT)
MAX1407 toc05
MAXIMUM INL vs. VDD (BIPOLAR MODE, T = +25C, FULLY DIFFERENTIAL INPUT)
4.5 4.0 MAXIMUM INL (LSB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 B A
MAX1407 toc06
5
5.0
4 MAXIMUM INL (LSB)
3
2
A B
1
0 2.7 2.9 3.1 VDD (V) 3.3 3.5
0 2.7 2.9 3.1 VDD (V) 3.3 3.5
A: GAIN = 1, UNBUFFERED MODE, 60sps B: GAIN = 1, UNBUFFERED MODE, 30sps
A: GAIN = 2, BUFFERED MODE, 60sps B: GAIN = 2, BUFFERED MODE, 30sps
MAXIMUM INL vs. TEMPERATURE (UNIPOLAR MODE, VDD = 3V, PSEUDO-DIFFERENTIAL INPUT)
MAX1407 toc07
MAXIMUM INL vs. TEMPERATURE (BIPOLAR MODE, VDD = 3V, FULLY DIFFERENTIAL INPUT)
4.5 4.0 MAXIMUM INL (LSB) 3.5 3.0 2.5 2.0 1.5 1.0 B A
MAX1407 toc08
5.0 4.5 4.0 MAXIMUM INL (LSB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 TEMPERATURE (C) A: GAIN = 1, UNBUFFERED MODE, 60sps B: GAIN = 1, UNBUFFERED MODE, 30sps B A
5.0
0.5 0 0 20 40 60 80 TEMPERATURE (C) A: GAIN = 2, BUFFERED MODE, 60sps B: GAIN = 2, BUFFERED MODE, 30sps
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
MAXIMUM INL vs. COMMON-MODE INPUT VOLTAGE (BIPOLAR MODE, BUFFERED MODE, VDD = 2.7V, 30sps, FULLY DIFFERENTIAL INPUT, T = +25C)
MAX1407 toc09
INL vs. FULLY DIFFERENTIAL INPUT VOLTAGE (BIPOLAR MODE, GAIN = 1, UNBUFFERED MODE, VCM = 0.625V, VDD = 3V, T = +25C)
1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0
MAX1407 toc10
3.0 2.5 MAXIMUM INL (LSB) B 2.0 1.5 A 1.0 0.5 0 0.3 0.5 0.7 0.9
2.0
-1.5 -2.0 1.1 -1.25 -0.75 -0.25 0.25 0.75 1.25 COMMON-MODE INPUT VOLTAGE (V) A: GAIN = 1 B: GAIN = 2 DIFFERENTIAL INPUT VOLTAGE (V)
INL vs. PSEUDO-DIFFERENTIAL INPUT VOLTAGE RANGE (UNIPOLAR MODE, GAIN = 1, UNBUFFERED MODE, VNEG = 0, VDD = 3V, T = +25C)
MAX1407 toc11
UNCORRECTED OFFSET ERROR vs. TEMPERATURE (UNBUFFERED MODE, VDD = 3V)
4.5 4.0 OFFSET ERROR (LSB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 B A
MAX1407 toc12
2.0 1.5 1.0 0.5 INL (LSB) 0 -0.5 -1.0 -1.5 -2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL VOLTAGE (V)
5.0
0
20
40
60
80
TEMPERATURE (C) A: GAIN = 1, UNIPOLAR MODE B: GAIN = 2, BIPOLAR MODE
10
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1407 toc13 MAX1407 toc14
MAX1407/MAX1408/MAX1409/MAX1414
GAIN ERROR vs. TEMPERATURE
0.12 0.11 B GAIN ERROR (%) 0.10 D 0.09 0.08 0.07 0.06 0 20 40 60 80 TEMPERATURE (C) A: GAIN = 1, UNIPOLAR MODE, UNBUFFERED MODE B: GAIN = 1, BIPOLAR MODE, UNBUFFERED MODE C: GAIN = 2, UNIPOLAR MODE, BUFFERED MODE D: GAIN = 2, BIPOLAR MODE, BUFFERED MODE A C % DEVIATION VDD = 3V 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -40
REFERENCE VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX1407 toc15
VREF = 1.24406V IREF = 0
1.24410 1.24405 REFERENCE VOLTAGE (V) 1.24400 1.24395 1.24390 1.24385 1.24380
-15
10
35
60
85
0
200
400
600
800
1000
1200
TEMPERATURE (C)
SOURCE CURRENT (A)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1407 toc16
DAC OFFSET ERROR vs. TEMPERATURE
MAX1407 toc17
DAC OFFSET ERROR vs. SUPPLY VOLTAGE
IDLE MODE -4.425 -4.450 OFFSET ERROR (mV) -4.475 -4.500 -4.525 -4.550 -4.575 -4.600
MAX1407 toc18
1.24412 1.24410 REFERENCE VOLTAGE (V) 1.24408 1.24406 1.24404 1.24402 1.24400 1.24398
NO LOAD
-3.4 -3.6 -3.8 OFFSET ERROR (mV) -4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -5.2
IDLE MODE
-4.400
2.70
2.85
3.00
3.15
3.30
3.45
3.60
-40
-15
10
35
60
85
2.70
2.85
3.00
3.15
3.30
3.45
3.60
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
DAC GAIN ERROR vs. TEMPERATURE
MAX1407 toc19
DAC GAIN ERROR vs. SUPPLY VOLTAGE
MAX1407 toc20
DAC INTEGRAL NONLINEARITY vs. DIGITAL CODE (AVDD = 2.7V)
MAX1407 toc21
0.15 0 -0.15 -0.30 GAIN ERROR (LSB) -0.45 -0.60 -0.75 -0.90 -1.05 -1.20 -1.35 -1.50
IDLE MODE
0.10 0.05 GAIN ERROR (LSB) 0
0.15 0.10 0.05 INL (LSB) 0
IDLE MODE
-0.05 -0.10 -0.15
-0.05 -0.10 INTERNAL REF USED -0.15 2.70 2.85 3.00 3.15 3.30 3.45 3.60 0 100 200 300 400 500 600 700 800 9001000 1100 CODE SUPPLY VOLTAGE (V)
INTERNAL REF USED -40 -15 10 35 60 85
-0.20
TEMPERATURE (C)
DAC INTEGRAL NONLINEARITY vs. DIGITAL CODE (AVDD = 3.6V)
MAX1407 toc22
DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE (AVDD = 2.7V)
MAX1407 toc23
DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE (AVDD = 3.6V)
0.075 0.050 DNL (LSB) 0.025 0 -0.025 -0.050 -0.075 -0.100
MAX1407 toc24
0.15 0.10 0.05
0.100 0.075 0.050 DNL (LSB)
0.100
INL (LSB)
0.025 0 -0.025 -0.050
0
-0.05 -0.10 -0.15 0 100 200 300 400 500 600 700 800 9001000 1100 CODE
-0.075 -0.100 0 100 200 300 400 500 600 700 800 900 1000 1100 CODE
0 100 200 300 400 500 600 700 800 900 1000 1100 CODE
DAC LARGE-SIGNAL OUTPUT STEP RESPONSE
MAX1407 toc25
CS 2V/DIV
OUT_ 500mV/DIV
VREF = 1.25V, AVDD = 3.0V, RL = 0
12
______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, MAX1407 used, TA = +25C, unless otherwise noted.)
DAC OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
OUTPUT AT FULL SCALE NO LOAD DAC BUFFER IN UNITY GAIN
MAX1407 toc26
DAC OUTPUT VOLTAGE vs. SOURCE CURRENT
OUTPUT AT FULL SCALE DAC BUFFER IN UNITY GAIN
MAX1407 toc27
DAC OUTPUT VOLTAGE vs. SINK CURRENT
MAX1407 toc28
1.2450
1.30 1.25 DAC OUTPUT VOLTAGE (V) 1.20 1.15 1.10 1.05
1.80 1.75 DAC OUTPUT VOLTAGE (V) 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 0 5 10 15 20 25 30 35
DAC OUTPUT VOLTAGE (V)
1.2445
1.2440
1.2435
1.2430 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
1.00 0 1 2 3 4 5 6 LOAD CURRENT (mA)
40
SINK CURRENT (A)
DAC OUTPUT VOLTAGE vs. TEMPERATURE
MAX1407 toc29
VOLTAGE MONITOR THRESHOLD vs. TEMPERATURE
MAX1407 toc30
0.15 0.12 DAC OUTPUT VOLTAGE (%) 0.09 0.06 0.03 0 -0.03 -0.06 -0.09 -0.12 -0.15 -40 -15 10 35 60 VREF = 1.24406V IREF = 0
0.10 0.05 0 % DEVIATION -0.05 -0.10 -0.15 -0.20 -0.25 V2.7V_THRESHOLD = 2.75V V1.8V_THRESHOLD = 1.865V
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
13
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Pin Description
MAX1407 MAX1414 1 -- -- 2 3 -- 4 -- 5 MAX1408 -- 1 -- 2 -- 3 -- 4 5 MAX1409 -- -- 1 -- -- -- 2 -- 3 PIN FB2 IN7 FB1 D0 FB1 IN6 OUT1 IN4 IN0 FUNCTION Force/Sense DAC2 Feedback Input Analog Input. Analog input to the negative mux only. Force/Sense DAC1 Feedback Input Digital Output. Three-state general-purpose digital output. Force/Sense DAC1 Feedback Input Analog Input. Analog input to the negative mux only. Force/Sense DAC1 Output Analog Input. Analog input to the positive mux only. Analog Input. Analog input to both the positive and negative mux. 1.25V Reference Buffer Output/External Reference Input. Reference voltage for the ADC and the DAC. Connect a 4.7F capacitor to REF between REF and AGND. Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate. Analog Supply Voltage PLL Capacitor Connection Pin. Connect an 18nF ceramic capacitor between CPLL and AVDD. Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from Sleep mode to Standby mode when WU1 is asserted. Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from Sleep mode to Standby mode when WU2 is asserted. Active-Low RESET Output. It remains low while AVDD is below the threshold and stays low for a timeout period after AVDD rises above the threshold. RESET is an open-drain output. Analog Input. Analog input to both the positive and negative mux. Analog Input. Analog input to both the positive and negative mux. Programmable Shutdown Output. Goes low in Sleep mode. Active-Low Data Ready Output. A logic low indicates that a new conversion result is available in the Data register. DRDY returns high upon completion of a full output word read operation. DRDY also signals the end of an ADC offset-calibration. 2.4576MHz Clock Output. FOUT can be used to drive the input clock of a P. 32kHz Crystal Output. Connect a 32kHz crystal between CLKIN and CLKOUT. 32kHz Crystal Input. Connect a 32kHz crystal between CLKIN and CLKOUT.
6
6
4
REF
7 8 9 10 11
7 8 9 10 11
5 6 7 8 9
AGND AVDD CPLL WU1 WU2
12 13 14 15
12 13 14 15
10 -- -- --
RESET IN1 IN2 SHDN
16
16
--
DRDY
17 18 19
17 18 19
11 12 13
FOUT CLKOUT CLKIN
14
______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
Pin Description (continued)
MAX1407 MAX1414 20 21 22 MAX1408 20 21 22 MAX1409 14 15 16 PIN INT DOUT DIN FUNCTION Active-Low Interrupt Output. INT goes low when the PLL output is ready, when the signal-detect comparator is tripped, or when the alarm is triggered. Serial Data Output. DOUT outputs serial data from the internal shift register on SCLK's falling edge. When CS is high, DOUT is three-stated. Serial Data Input. Data on DIN is written to the input shift register and is clocked in at SCLK's rising edge when CS is low. Serial Clock Input. Apply an external serial clock to transfer data to and from the device. This serial clock can be continuous, with data transmitted in a train of pulses, or intermittent while CS is low. Active-Low Chip-Select Input. CS is used to select the active device in systems with more than one device on the serial bus. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is three-stated. Digital Ground. Reference point for digital circuitry. Digital Supply Voltage Analog Input. Analog input to both the positive and negative mux. Force/Sense DAC2 Output Analog Input. Analog input to the positive mux only.
MAX1407/MAX1408/MAX1409/MAX1414
23
23
17
SCLK
24
24
18
CS
25 26 27 28 --
25 26 27 -- 28
19 20 -- -- --
DGND DVDD IN3 OUT2 IN5
Detailed Information
The MAX1407/MAX1408/MAX1409/MAX1414 are lowpower, general-purpose, multichannel DAS featuring a multiplexed fully differential 16-bit analog-to-digital converter (ADC), 10-bit force/sense digital-to-analog converters (DAC), a real-time clock (RTC) with an alarm, a bandgap voltage reference, a signal detect comparator, two power-supply voltage monitors, wakeup control circuitry, and a high-frequency phase-locked loop (PLL) clock output all controlled by a 3-wire serial interface. (See Table 1 for the MAX1407/MAX1408/
MAX1409/MAX1414 feature sets and Figures 1, 2, 3 for the Functional Diagrams). These DAS directly interface to various sensor outputs and once configured provide the stimulus, conditioning, and data conversion, as well as microprocessor support. Figure 4 is a Typical Application Circuit for the MAX1407/MAX1414. The 16-bit ADC is capable of programmable continuous conversion rates of 30Hz or 60Hz and gains of 1/3, 1, and 2V/V to suit applications with different power and dynamic range constraints. The force/sense DACs provide 10-bit linearity for precise sensor applications.
Table 1. MAX1407/MAX1408/MAX1409/MAX1414 Feature Sets
PART ADC AUXILIARY ANALOG INPUTS 4 4 8 1 FORCE/ SENSE DAC 2 2 0 1 THREESTATE DIGITAL OUTPUT Yes Yes Yes No COMPARATOR THRESHOLD (mV) 0 50 0 0 RTC ADC DATA READY (DRDY) Yes Yes Yes No EXTERNAL POWERSUPPLY SHUTDOWN CONTROL Yes Yes Yes No ADC DIFFERENTIAL INPUT MUX 8 8 8 4
MAX1407 MAX1414 MAX1408 MAX1409
Yes Yes Yes Yes
______________________________________________________________________________________
15
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
AVDD CPLL FOUT CLKIN CLKOUT DVDD
CS SCLK DIN DOUT
SERIAL INTERFACE
2.4576MHz PLL
32.768kHz OSCILLATOR
RTC AND ALARM
WU2 WAKE-UP LOGIC WU1 SHDN
MAX1407/MAX1414 OUT2 OUT1 8:1 INPUT MUX REF AVDD BUF BUF PGA 16-BIT ADC COMPARATOR INTERRUPT GENERATOR INT DRDY
IN3 IN2 IN1 IN0
DIGITAL OUTPUT
D0
FB2 FB1 IN3 IN2 IN1 IN0 REF AGND
8:1 INPUT MUX
1.8V/2.7V P SUPERVISORS RESET GENERATOR
1.25V BANDGAP REFERENCE BUF
10-BIT DAC
OUT1 FB1
10-BIT DAC
OUT2 FB2
AGND
RESET
REF
DGND
*MAX1414 HAS A +50mV SIGNAL-DETECT COMPARATOR THRESHOLD.
Figure 1. MAX1407/MAX1414 Functional Diagram
With the use of two external resistors, the DAC output can go from 0.05V to AV DD - 0.2V. The ADCs and DACs both utilize a precise low-drift 1.25V internal bandgap reference for conversions and setting of the full-scale range. For applications that require increased accuracy, power-down the internal reference and connect an external reference at REF. The RTC is leap year compensated until 9999 and provides an alarm function that can be used to wake-up the system or cause an interrupt at a predefined time. The power-supply voltage monitors detect when AV DD falls below a trip threshold voltage at either +1.8V or +2.7V causing the reset to be asserted. The 4-wire serial interface is used to communicate directly between SPI, QSPI, and MICROWIRE devices for system configuration and readback functions.
Analog Mux
The MAX1407/MAX1408/MAX1414 include a dual 8 to 1 multiplexer for the positive and negative inputs of the ADC. The MAX1409 has a dual 4 to 1 multiplexer at the inputs of the ADC. Figures 1, 2, and 3 illustrate which signals are present at the inputs of each multiplexer for the MAX1407/MAX1408/MAX1409/MAX1414. The MUXP and MUXN bits of the MUX register choose which inputs will be seen at the input to the ADC (Tables 4 and 5) and the signal-detect comparator. See the MUX Register description under the On-Chip Registers section for multiplexer functionality.
Input Buffers
The MAX1407/MAX1408/MAX1409/MAX1414 provide input buffers to isolate the analog inputs from the capacitive load presented by the ADC modulator (Figure 5 and 6). The buffers are chopper stabilized to reduce the effect of their DC offsets and low-frequency noise. Since the buffers can represent more than 25% of the total analog power dissipation (typically 220A), they may be shut down in applications where minimum power dissipation is required and the capacitive input load is not a concern (see ADC and Power1 Registers). Disable the buffers in applications where the inputs must operate close to AGND or above +1.4V. The buffers are individually enabled or disabled.
Analog Input Protection
Internal protection diodes clamp the analog input to AVDD and AGND, which allow the channel input pins to swing from AGND - 0.3V to AVDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed AVDD by more than 50mV or be lower than AGND by 50mV.
16
______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
AVDD CPLL FOUT CLKIN CLKOUT DVDD
CS SCLK DIN DOUT
SERIAL INTERFACE
2.4576MHz PLL
32.768kHz OSCILLATOR
RTC AND ALARM
WU2 WAKE-UP LOGIC WU1 SHDN
IN5 IN4 IN3 IN2 IN1 IN0 REF AVDD
COMPARATOR 8:1 INPUT MUX
INTERRUPT GENERATOR
INT DRDY
BUF PGA BUF 16-BIT ADC
DIGITAL OUTPUT
D0
IN7 IN6 IN3 IN2 IN1 IN0 REF AGND 8:1 INPUT MUX
1.8V/2.7V P SUPERVISORS RESET GENERATOR
1.25V BANDGAP REFERENCE MAX1408 BUF
AGND
RESET
REF
DGND
Figure 2. MAX1408 Functional Diagram
AVDD
CPLL
FOUT
CLKIN CLKOUT
DVDD
CS SCLK DIN DOUT
SERIAL INTERFACE
2.4576MHz PLL
32.768kHz OSCILLATOR
RTC AND ALARM
WU2 WAKE-UP LOGIC WU1
OUT1 IN0 REF AVDD BUF 4:1 INPUT MUX BUF
COMPARATOR
INTERRUPT GENERATOR
INT
PGA
16-BIT ADC
FB1 IN0 REF AGND 4:1 INPUT MUX
1.8V/2.7V P SUPERVISORS RESET GENERATOR
1.25V BANDGAP REFERENCE BUF
10-BIT DAC
OUT1 FB1
MAX1409
AGND
RESET
REF
DGND
Figure 3. MAX1409 Functional Diagram ______________________________________________________________________________________ 17
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
LX OUT RST LX 10F MAX1833 BATT GND SHDN 18nF 0.1F 0.1F 0.1F VDD = 3.3V OR VBAT
CPLL SHDN IN0
AVDD
DVDD RESET CLKIN 32.768kHz CLKOUT RESET
VDD
P/C
VBAT
10F 4.7F RL
REF
IN1 RT MAX1407 MAX1414 OUT1 RF FB1 SENSOR WE RE CE
FOUT CS SCLK DIN DOUT INT DRDY WU1
CLKIN OUTPUT SCK MOSI MISO INPUT INPUT I/O I/O
FB2
WU2
OUT2 AGND DGND VSS
Figure 4. MAX1407/MAX1414 Typical Application Circuit
REXT CEXT
RMUX CPIN CST
RIN CAMP CSAMPLE CC
Figure 5. Analog Input--Buffered Mode
Buffered Mode When used in buffered mode, the buffers isolate the inputs from the sampling capacitors. The samplingrelated gain error is dramatically reduced since only a
small dynamic load is present from the chopper. The multiplexer exhibits an input leakage current of 0.5nA (typ). With high-source resistances, this leakage current may result in a large DC offset error.
18
______________________________________________________________________________________
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
ADC Offset Calibration
REXT CEXT RMUX CPIN RSW CST CSAMPLE CC
MAX1407/MAX1408/MAX1409/MAX1414
Figure 6. Analog Input--Unbuffered Mode
Unbuffered Mode When used in unbuffered mode, the switched capacitor sampling front end of the modulator presents a dynamic load to the driving circuitry. The size of the internal sampling capacitor and the input sampling frequency (Figure 6) determines the dynamic load (see Dynamic Input Impedance section). As the gain increases, the input sampling capacitance also increases. Since the MAX1407/MAX1408/MAX1409/MAX1414 sample at a constant rate for all gain settings, the dynamic load presented by the inputs varies with the gain setting.
PGA Gain
An integrated programmable-gain amplifier (PGA) provides three user-selectable gains: +1/3V/V, +1V/V, and +2V/V to maximize the dynamic range of the ADC. Bits GAIN1 and GAIN0 set the desired gain (see ADC Register). The gain of +1/3V/V allows the direct measurement of the supply voltage through an internal multiplexer input or through an auxillary input.
The MAX1407/MAX1408/MAX1409/MAX1414 are capable of performing digital offset correction to eliminate changes due to power-supply voltage or system temperature. At the end of a calibration cycle, a 16-bit calibration value is stored in the Offset register in two's compliment format. After completing a conversion, the MAX1407/MAX1408/MAX1409/MAX1414 subtract the calibration value from the ADC conversion result and write the offset compensated data to the Data register (see Offset Register section). Either a positive or negative offset can be calibrated. During offset calibration, DRDY will go high. DRDY goes low after calibration is complete. The offset register can be programmed to skew the ADC offset with a maximum range from -215 to (+215 - 1)LSBs, e.g., if the programmed 2's complement value is +2LSB (-2LSB), this translates to a -2LSB (+2LSB) shift in bipolar mode or a -4LSB (+4LSB) shift in unipolar mode.To maintain optimum performance, recalibrate the ADC if the temperature changes by more than 20C. Offset calibration should also be performed after any changes in PGA gain, bipolar/unipolar input range, buffered/unbuffered mode, or conversion speed. During calibration, the two mulitplexers will be disabled and the inputs to the ADC will internally be shorted to a common-mode voltage.
ADC Digital Filter
The on-chip digital filter processes the 1-bit data stream from the modulator using a SINC3 filter function. The SINC3 filters settle in three data word periods. The settling time is 3/60Hz or 50ms (for RATE bit in ADC register set to 1) and 3/30Hz or 100ms (for RATE bit set to "0").
ADC Modulator
The MAX1407/MAX1408/MAX1409/MAX1414 perform analog-to-digital conversions using a single-bit, second-order, switched-capacitor delta-sigma modulator. The delta-sigma modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. The pulse train is then processed by a digital decimation filter. The modulator provides 2nd-order frequency shaping of the quantization noise resulting from the single bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. The modulator operates at one of two different sampling rates resulting in an output data rate of either 30Hz or 60Hz (see ADC Register).
ADC Digital Filter Characteristics
The transfer function for a SINC3 filter function is that of three cascaded SINC1 filters. This can be described in the Z-domain by: 1 - z -N 1 H( z) = -1 N 1- z
( (
) )

3
and in the frequency domain by: sin N M 1 H( ) = N sin M
3
where N, the decimation factor, is the ratio of the modulator frequency fM to the output frequency fN.
______________________________________________________________________________________ 19
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
0 -20 -40 GAIN (dB) -60 -80 -100 -120 -140 -160 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz)
Figure 7. Frequency Response of the SINC3 Filter (Notch at 60Hz)
Figure 7 shows the filter frequency response. The SINC3 characteristic cutoff frequency is 0.262 times the first notch frequency. This results in a cutoff frequency of 15.72Hz for a first filter notch frequency of 60Hz (output data rate of 60Hz). The response shown in Figure 7 is repeated at either side of the digital filter's sample frequency (f M ) (f M = 15.36kHz for 30Hz and f M = 30.72kHz for 60Hz) and at either side of the related harmonics (2fM, 3fM,....). The output data rate for the digital filter corresponds with the positioning of the first notch of the filter's frequency response. Therefore, for the plot of Figure 7 where the first notch of the filter is at 60Hz, the output data rate is 60Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch frequency. The SINC 3 filter provides an attenuation of better than 100dB at these notches. For step changes at the input, enough settling time must be allowed before valid data can be read. The settling time depends upon the output data rate chosen for the filter. The settling time of the SINC3 filter to a fullscale step input can be up to four times the output data period, or three times if the step change is synchrozied with FSYNC.
Shorting FB1(2) and OUT1(2) configures the DAC in a unity-gain setting. Connecting resistors in a voltagedivider configuration between OUT1(2), FB1(2), and GND sets a different closed-loop gain for the output amplifier (see the Applications Information section). The DAC output amplifier typically settles to 1/2LSB from a full-scale transition within 65s, when it is connected in unity gain and loaded with 12k in parallel with 200pF. Loads less than 2k may degrade performance. See the Typical Operating Characteristics section for the source-and-sink capabilty of the DAC output. The MAX1407/MAX1409/MAX1414 feature a softwareprogrammable shutdown mode for the DACs that reduce the total power consumption when they are not used. The two DACs can be powered-down independently or simultaneously by clearing the DA1E and DA2E bits (see Power1 Register). DAC outputs OUT1 and OUT2 go high impedance when powered down. The DACs are automatically powered up and ready for a conversion when Idle or Run mode is entered.
Voltage Monitors
The MAX1407/MAX1408/MAX1409/MAX1414 include two on-board voltage monitors. When AVDD is below the RESET trip threshold, RESET goes low and the RST bit of the Status register is set to "1". When AVDD is below the Low VDD trip threshold, the LVD bit of the Status register is set to 1.
RESET Voltage Monitor The RESET voltage monitor is powered up at all times (provided that VM = 0 and LVDE = 1 or VM = 1 and LSDE = 1). A threshold voltage of either +1.8V or +2.7V may be selected for the RESET voltage monitor (see Power2 Register). At initial power-up, the RESET trip threshold is set to 2.7V. If the RESET voltage monitor is tripped, the RST bit of the status register is set to "1" and RESET goes low. RESET is held low for 1.54 seconds (typ) after AVDD rises above the RESET voltage monitor threshold. If AVDD is no longer below the RESET threshold, reading the Status register will clear RST.
Low VDD Voltage Monitor When the device is operating in Run, Idle, or Standby mode (see Power Modes) and AVDD goes below +2.7V, the low VDD monitor trips, indicating that the supply voltage is below the safe minimum for proper operation. When tripped, the Low VDD Voltage Monitor sets the LVD bit of the Status register to 1. If AVDD is no longer below +2.7V, reading the Status register will clear LVD. The low VDD monitor is powered down in Sleep mode. When it is powered down, the LVD bit stays unchanged. The LVD is cleared if it is read in Sleep mode.
Force/Sense DAC (MAX1407/MAX1409/MAX1414)
The MAX1407/MAX1414 incorporate two 10-bit force/ sense DACs while the MAX1409 has one. The DACs use a precise 1.25V internal bandgap reference for setting the full-scale range. Program the DAC1 and DAC2 registers through the serial interface to set the output voltages of the DACs seen at OUT1 and OUT2.
20
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
Internal/External Reference
The MAX1407/MAX1408/MAX1409/MAX1414 have an internal low-drift +1.25V reference used for both ADC and DAC conversion. The buffered reference output can be used as a reference source for other devices in the system. The internal reference requires a 4.7F lowESR ceramic capacitor or tantalum capacitor connected between REF and AGND. For applications that require increased accuracy, power-down the internal reference by writing a 0 to the REFE bit of the Power1 register and connect an external reference source to REF. The valid external reference voltage range is 1.25V 100mV. modes except the sleep mode (see Power Modes). To reactivate the PLL, the following conditions must be met: AVDD is greater than the low VDD voltage monitor threshold, RESET is deasserted, and the PLLE bit is equal to "1". FOUT is enabled 31.25ms (tDFON) after the PLL is activated. At initial power-up, the PLL is enabled. If RESET is asserted while the PLL is running, the PLL does not shut down.
MAX1407/MAX1408/MAX1409/MAX1414
Real-Time Clock (RTC)
The integrated RTC provides the current second, minute, hour, date, month, day, year, century, and millenium information. An internally generated reference clock of 1.024kHz (derived from the 32.768kHz crystal) drives the RTC. The RTC operates in either 24-hour or 12-hour format with an AM/PM indicator (see RTC_Hour Register). An internal calendar compensates for months with less than 31 days and includes leap year correction through the year 9999. The RTC operates from a supply voltage of +1.8V to +3.6V and consumes less than 1A current.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or resonator) connected between CLKIN and CLKOUT with an operating frequency of 32.768kHz. This oscillator is used for the RTC, alarm, signal-detect comparator, and PLL. The oscillator is operational down to 1.8V. In any crystal-based oscillator circuit, the oscillator frequency is based on the characteristics of the crystal. It is important to select a crystal that meets the design requirements, especially the capacitive load (CL) that must be placed across the crystal pins in order for the crystal to oscillate at its specified frequency. CL is the capacitance that the crystal needs to "see" from the oscillator circuit; it is not the capacitance of the crystal itself. The MAX1407/MAX1408/MAX1409/MAX1414 have 6pF of capacitance across the CLKIN and CLKOUT pins. Choose a crystal with a 32.768kHz oscillation frequency and a 6pF capacitive load such as the C002RX32-E from Epson Crystal. Using a crystal with a CL that is larger than the load capacitance of the oscillator circuit will cause the oscillator to run faster than the specified nominal frequency of the crystal. Conversely, using a crystal with a CL that is smaller than the load capacitance of the oscillator circuit will cause the oscillator to run slower than the specified nominal frequency of the crystal.
Time of Day Alarm
The MAX1407/MAX1408/MAX1409/MAX1414 offer a time of day alarm which generates an interrupt when the RTC reaches a preset combination of seconds, minutes, hours, and day (see Alarm Registers). In addition to setting a "single-shot" alarm, the Time of Day Alarm can also be programmed to generate an alarm every second, minute, hour, day, or week. "Don't care" states can be inserted into one or more fields if it is desired for them to be ignored for the alarm condition. The Time of Day Alarm wakes up the device into Standby mode if it is in Sleep mode. The Time of Day Alarm operates from a supply voltage of +1.8V to +3.6V.
Phase-Locked Loop (PLL) and FOUT
An on-board phase-locked loop generates a 2.4576MHz clock at FOUT from the 32.768kHz crystal oscillator. FOUT can be used to clock a P or other digital circuitry. Connect an 18nF ceramic capacitor from CPLL to AVDD to create the 2.4576MHz clock signal at FOUT. To power down the PLL, clear PLLE in the Power2 register (see Power2 Register) or write to the Sleep register. FOUT will be active for 1.95ms (tDFOF) after receiving either power-down command and then go low. This provides extra clock signals to the P to complete a shutdown sequence. The PLL is active in all
I Interrupt (INT) INT indicates one of three conditions. After receiving a valid interrupt (INT goes low), read the Status register and the Al_Status register (if the alarm is enabled) to identify the source of the interrupt. The three sources of interrupts are from the CLK, SDC, and ALIRQ bits.
PLL Ready On power-up, INT is high. 7.82ms (tDFI) after the PLL output appears on FOUT, INT goes low (see Figure 15). The CLK bit of the Status register is set to "1" after FOUT is enabled. Reading the Status register clears the CLK bit. INT remains low until the device detects a start bit through the serial interface from the P. The purpose of this interrupt is to inform the P that the FOUT clock signal is present.
______________________________________________________________________________________
21
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
CS
SCLK
DIN
1 0 A4 A3 A2 A1 A0 x D7 D6 D5 D4 D3 D2 D1 D0 ADC CONV
1 1 A4 A3 A2 A1 A0 x
DOUT DRDY
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 8. ADC Conversion Timing Diagram
Signal Detect The INT pin will also go low and stay low when the differential voltage on the selected analog inputs exceeds the signal-detect comparator trip threshold (0mV for the MAX1407/MAX1408/MAX1409 and 50mV for the MAX1414). This will latch the SDC bit of the Status register to one. Additional signal detect interrupts cannot be generated unless the SDC bit is cleared. To clear the SDC bit, the Status register must be read and the input must be below the signal-detect threshold. Powering down the signal detect-comparator without reading the Status register will also clear the SDC bit. Similar to the power-up case, INT goes high when the device detects a start bit through the serial interface from the P. Time of Day Alarm If the device is in Sleep mode, the alarm will wake up the device and set the ALIRQ bit. INT is asserted when the PLL is turned on. If an alarm occurs while the device is awake (BIASE = 1), the ALIRQ bit will be set and INT will go low. INT remains low until the device detects a start bit through the serial interface from the P. ALIRQ is reset to 0 when any alarm register is read or written to.
SHDN is not available on the MAX1409. Note: Entering Sleep mode automatically sets PLLE and SHDE to 0. Any wake-up event will cause SHDN to go high. (See Wake-Up section.)
D Data Ready (DRDY) This pin will go low and stay low upon completion of an ADC conversion or end of an ADC calibration. This signals the P that a valid conversion or calibration result has been written to the DATA or the OFFSET register. The DRDY pin goes high either when the P has finished reading the conversion/calibration result on the last rising edge of SCLK (see Figure 8), or when the next conversion result is about to be written to the DATA register. When no read operation is performed, DRDY pulses at 60Hz with a pulse high time of 162.76s (or 30Hz with a pulse high time of 325.52s) DRDY is not available on the MAX1409. To see when the ADC has completed a normal conversion or a calibration conversion for the MAX1409, check the status of the ADD bit in the Status register.
Serial Digital Interface
The SPI/QSPI/MICROWIRE-serial interface consists of chip select (CS), serial clock (SCLK), data in (DIN), and data out (DOUT) (See Figure 9). The serial interface provides access to 29 on-chip registers, allowing control to all the power modes and functional blocks, including the ADCs, DACs, and RTC. Table 2 lists the address and read/write accessibility of all the registers. A logic high on CS three-states DOUT and causes the MAX1407/MAX1408/MAX1409/MAX1414 to ignore any signals on SCLK and DIN. To clock data into or out of the internal shift register, drive CS low. SCLK synchronizes the data transfer. The rising edge of SCLK clocks DIN into the shift register, and the falling edge of SCLK
S Shutdown (SHDN) SHDN is an active-low output that can be used to control an external power supply. Powering up the PLL (PLLE = 1) or writing a "1" to the SHDE bit of the Power2 register causes SHDN to go high. SHDN goes low when the SHDE bit is set to 0 only if the PLL is powered down (PLLE = 0). The SHDN output stays high for 2.93ms (tDPD) after receiving a power-down command, allowing the external power supply to stay alive so that the P can properly complete a shutdown sequence.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
clocks DOUT out of the shift register. DIN and DOUT are transferred as MSB first (data is left justified). Figure 10 shows detailed serial interface timing. All communication with the MAX1407/MAX1408/ MAX1409/MAX1414 begins with a command byte on DIN, where the first logic 1 on DIN will be recognized as the START bit (MSB) for the command byte (Table 3). The following seven clock cycles load the command into a shift register. These seven bits specify which of the registers will be accessed, whether a read or write operation will take place, and the length of the subsequent data (0-bit, 8-bit, 16-bit, or burst mode). Idle DIN low between writes to the MAX1407/MAX1408/MAX1409/ MAX1414. Figures 11-14 show the read and write timing for 8- and 16-bit data. Data is updated on the last rising edge of the SCLK in the command word. CS should not go high between data transfers. If CS is toggled before the end of a write or read operation, the device can enter an incorrect mode. Clock in 72 zeros to clear this state and re-arm the serial interface. After loading the command byte into the shift register, additional clocks shift out data on DOUT for a read and shift in data on DIN for a write operation.
MAX1407/MAX1408/MAX1409/MAX1414
CLKIN 32.768kHz CLKOUT FOUT RESET CLKIN RESET P/C
CS MAX1407 MAX1408 MAX1409 MAX1414 SCLK DIN DOUT INT DRDY WU1 WU2
OUTPUT SCK MOSI MISO INPUT INPUT I/O I/O
DRDY NOT AVAILABLE ON MAX1409
Figure 9. SPI/QSPI Interface Connections
CS tCSS tCYC tCH
*** tCSH tCL tCSH *** tDS tDH
SCLK
DIN tDV DOUT
*** tDO *** tTR
Figure 10. Detailed Serial Interface Timing ______________________________________________________________________________________ 23
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
CS
SCLK
DIN
1
0
A4
A3
A2
A1
A0
x
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
DOUT
Figure 11. Serial Interface 16-Bit Write Timing Diagram
CS
SCLK
DIN
1
0
A4
A3
A2
A1
A0
x
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Figure 12. Serial Interface 8-Bit Write Timing Diagram
CS
SCLK
DIN
1
1
A4
A3
A2
A1
A0
x
DOUT
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
Figure 13. Serial Interface 16-Bit Read Timing Diagram
CS allows the SCLK, DIN, and DOUT signals to be shared among several devices. When short on processor I/O pins, connect CS to DGND, and operate the serial digital interface in CPOL = 1, CPHA = 1 or CPOL = 0, CPHA = 0 modes using SCLK, DIN, and DOUT.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
CS
SCLK
DIN
1
1
A4
A3
A2
A1
A0
x
DOUT
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. Serial Interface 8-Bit Read Timing Diagram
Table 2. Register Summary and Addressing
TARGET REGISTER ADC Register MUX Register Data Register Offset Register DAC1 Register DAC2 Register Status Register Al_Burst Register Al_Sec Register Al_Min Register Al_Hour Register Al_Day Register Al_Status Register Alarm/Clock_Ctrl Register RTC_Burst Register R/W ACCESS R/W R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W ADD4:ADD0 00000 00001 00010 00011 00100 00101 00110 01000 01001 01010 01011 01100 01101 01110 01111 TARGET REGISTER RTC_Sec Register RTC_Min Register RTC_Hour Register RTC_Date Register RTC_Month Register RTC_Day Register RTC_Year Register RTC_Century Register Power1 Register Power2 Register Sleep Register Standby Register Idle Register Run Register R/W ACCESS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W ADD4:ADD0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101
Table 3. Command Byte Format
COMMAND Write Read BIT 7 (MSB) 1 1 BIT 6 0 1 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) X X ADD4:ADD0 (see Table 2) ADD4:ADD0 (see Table 2)
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
On-Chip Registers
ADC REGISTER (00000)
FIRST BIT (MSB) NAME DEFAULTS MODE 0 RATE 0 GAIN1 0 GAIN0 0 BUFP 0 BUFN 0 BIP 0 (LSB) STA1 0
MODE: Conversion Mode bit. A logic zero selects a normal ADC conversion, while a logic 1 selects an offset calibration conversion. After completing a calibration conversion, MODE automatically resets to zero. RATE: Conversion Rate bit. A logic zero selects a 30Hz conversion rate while a logic 1 selects a 60Hz conversion rate. GAIN1, GAIN0: Gain bits. The Gain bits select the PGA gain. For an ADC gain of +1/3, +1, and 2V/V, [GAIN1 GAIN0] are 00, 01, and 10, respectively. BUFP: Positive Buffer bit. When this bit is 0, the positive input buffer is bypassed and powered down. When this bit is 1 and the BUFE bit in the Power1 register is 1, the positive input buffer drives the ADC input sampling capacitors. BUFN: Negative Buffer bit. When this bit is 0, the negative input buffer is bypassed and powered-down. When this bit is 1 and the BUFE bit in the Power1 register is 1, the negative input buffer drives the ADC input sampling capacitors.
BIP: Unipolar/Bipolar bit. A logic zero selects unipolar mode while a logic 1 selects bipolar mode. STA1: Start bit. Setting STA1 to a logic 1 resets the registers inside the ADC filter, updates the ADC configuration according to the ADC register, and initiates an analog-to-digital conversion or offset calibration. The initial conversion requires three cycles for valid output data, and each subsequent conversion cycle will output valid data. After completing the intial conversion, STA1 automatically resets to 0; however, the ADC will continue to do conversions until it is powered down. Writing to the ADC register with STA1 set to 0 updates the ADC register without changing the ADC configuration and allows the ADC to continue conversions uninterrupted. This allows the ADC and MUX configuration to be updated simultaneously. See STA2 bit of the MUX register.
MUX REGISTER (00001)
FIRST BIT (MSB) NAME DEFAULTS MUXP2 0 MUXP1 0 MUXP0 0 MUXN2 0 MUXN1 0 MUXN0 0 DBIT 0 (LSB) STA2 0
MUXP2, MUXP1, MUXP0: Positive Multiplexer bits. MUXP[2:0] direct one-of-eight positive inputs to the positive input of the ADC. Table 4 relates the MUXP bits to the positive multiplexer inputs. MUXN2, MUXN1, MUXN0: Negative Multiplexer bits. MUXN[2:0] direct one-of-eight (one-of-four for the MAX1409) negative inputs to the negative input of the ADC. Table 5 relates the MUXN bits to the negative multiplexer inputs. DBIT: Digital Output bit. This bit controls the output state of D0. When the output buffer is enabled, D0 is low if Dbit is equal to 0, and high if Dbit is equal to 1. D0 is enabled by the D0E bit of the Power2 register.
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STA2: Start bit. Setting STA2 to a logic 1 updates the mux selection, resets the registers inside the ADC filter, updates the ADC configuration according to the ADC register, and initiates an analog-to-digital conversion. The initial conversion requires three cycles for valid output data, and each subsequent conversion cycle will output valid data. STA2 automatically resets to 0 after the initial conversion completes. The ADC will continue to do conversions until it is powered down. Writing to the MUX register with the STA2 bit set to 0, updates the MUX register and selection, but leaves the ADC configuration unchanged. The MUX input can be switched with the ADC continuously converting without the digital filter resetting.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Table 4. Positive Mux Decoding
POSITIVE MUX INPUT MAX1407/MAX1414 AVDD REF OUT1 IN0 IN1 IN2 IN3 OUT2 MAX1408 AVDD REF IN4 IN0 IN1 IN2 IN3 IN5 MAX1409 AVDD REF OUT1 IN0 -- -- -- -- MUXP2 0 0 0 0 1 1 1 1 MUXP1 0 0 1 1 0 0 1 1 MUXP0 0 1 0 1 0 1 0 1
Table 5. Negative Mux Decoding
NEGATIVE MUX INPUT MAX1407/MAX1414 AGND REF FB1 IN0 IN1 IN2 IN3 FB2 MAX1408 AGND REF IN6 IN0 IN1 IN2 IN3 IN7 MAX1409 AGND REF FB1 IN0 -- -- -- -- MUXN2 0 0 0 0 1 1 1 1 MUXN1 0 0 1 1 0 0 1 1 MUXN0 0 1 0 1 0 1 0 1
DATA REGISTER--Read-Only (00010)
FIRST BIT (MSB) ADC15 ADC7 ADC14 ADC6 ADC13 ADC5 ADC12 ADC4 ADC11 ADC3 ADC10 ADC2 ADC9 ADC1 ADC8 ADC0 (LSB)
The Data register contains the 16-bit result from the most recently completed ADC conversion. The data format is binary for unipolar mode and two's complement for bipolar mode. After power-up, the DATA register contains all zeros.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
OFFSET REGISTER (00011)
FIRST BIT (MSB) OFF15 OFF7 OFF14 OFF6 OFF13 OFF5 OFF12 OFF4 OFF11 OFF3 OFF10 OFF2 OFF9 OFF1 OFF8 OFF0 (LSB)
The Offset register contains the 16-bit result from the most recently completed ADC offset calibration. The data format is two's complement and is subtracted from the filter output before writing to the Data register. After power-up, the Offset register contains all zeros. Each change in ambient operating condition (power supply and temperature), PGA gain, bipolar/unipolar input range, buffered/unbuffered mode, or conversion speed requires an offset calibration. The offset for a given ADC configuration can be read and stored by the P to avoid ADC recalibration. When returning to an ADC configuration where the offset was stored, write back the stored offset to the Offset register. The stored offset stays valid as long as the ambient operating condition remains unchanged (within 20C).
Force Sense DAC Registers (MAX1407/MAX1409/MAX1414 only) Writing to the DAC1 register updates the output of DAC1. Writing to the DAC2 register updates the output of DAC2. The DAC data is 10-bit long and left justified. Follow the timing diagrams of Figure 11 and Figure 13 to program these registers. Writing a logic 0 to the DA1E or DA2E bit in the POWER2 register disables DAC1 or DAC2, respectively. At power-up, DAC1 and DAC2 are disabled.
DAC1 REGISTER (00100)
FIRST BIT (MSB) DAC1[9] DAC1[1] DAC1[8] DAC1[0] DAC1[7] x DAC1[6] x DAC1[5] x DAC1[4] x DAC1[3] x DAC1[2] x (LSB)
Writing to the DAC1 register will update the DAC1 output (OUT1). The output voltage in a unity gain configuration is VREF x N/(210), where N is the integer value of DAC1[9:0]
(0 to 1023), and VREF is the reference voltage for the DAC. The DAC1 data is 10-bit long and left justified. After power-up, the DAC1 register contains all zeros.
DAC2 REGISTER (00101)
FIRST BIT (MSB) DAC2[9] DAC2[1] DAC2[8] DAC2[0] DAC2[7] x DAC2[6] x DAC2[5] x DAC2[4] x DAC2[3] x DAC2[2] x (LSB)
Writing to the DAC2 register will update the DAC2 output (OUT2). The output voltage in a unity-gain configuration is VREF x N/(210), where N is the integer value of DAC2[9:0]
(0 to 1023), and VREF is the reference voltage for the DAC. The DAC2 data is 10-bit long and left justified. After power-up, the DAC2 register contains all zeros.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
STATUS REGISTER (00110)
FIRST BIT (MSB) NAME DEFAULT WU2 0 WU1 0 RST 1 LVD 1 SDC 0 CLK 0 ADD 0 (LSB) -- 0
MAX1407/MAX1408/MAX1409/MAX1414
WU2: Wake-Up2 status bit. When WU2 is pulled low, WU2 is set to a logic 1. Reading the Status register clears WU2, unless WU2 is still low. When WU2 is pulled low when the device is awake (not in Sleep mode), WU2 is cleared. WU1: Wake-Up1 status bit. When WU1 is pulled low, WU1 is set to a logic 1. Reading the Status register clears WU1, unless WU1 is still low. When WU1 is pulled low when the device is awake (not in Sleep mode), WU1 is cleared. RST: Reset status bit. When AVDD drops below the RESET Voltage Monitor trip threshold (+1.8V or +2.7V), RST is set to 1. This corresponds to the assertion of the RESET pin. Reading the Status register clears RST, unless AVDD is still below the RESET Voltage Monitor trip threshold. At power-up, RST is at a logic 1 until the Status register is read. LVD: Low VDD status bit. When AVDD drops below the Low VDD Voltage Monitor trip threshold (+2.7V), LVD is set to a logic 1. Reading the Status register clears LVD unless AVDD is still below 2.7V. At power-up, LVD is at a logic 1 until the Status register is read. When the Low VDD Voltage Monitor is powered down (LVDE = 0), the LVD bit stays unchanged. SDC: Signal-Detect Comparator status bit. SDC is set to "1" when the differential polarity voltage across the signal-detect comparator exceeds the signal-detect threshold (0mV for the MAX1407/MAX1408/MAX1409 and 50mV for the MAX1414). This corresponds to the assertion of the INT pin. Reading the Status register clears SDC unless the condition remains true. SDC is also reset to 0 when the signal-detect comparator is powered down (SDCE = 0). CLK: FOUT Clock Enable status bit. CLK is set to "1" after the FOUT clock pin has been enabled in tDFON milliseconds (see Figure 15). Reading the Status register clears the CLK bit. ADD: ADC Done Status bit. ADD is set to "1" to indicate that the ADC has completed either a normal conversion or a calibration conversion, and the conversion result is available to be read. This corresponds to the assertion of the DRDY pin. Reading either the Data or Offset register clears the ADD bit. Reading the Status register WILL NOT clear this bit.
Alarm Registers The Al_Sec, Al_Min, Al_Hour, Al_Day registers are programmed through the serial port to store the preset time data in binary-coded decimal format (BCD). See Table 6 for decimal to BCD conversion. These registers can be accessed individually or consecutively using burst mode (see Al_Burst Register section). To enable the alarm, set the AE bit of the Alarm/Clock_Ctrl Register to 1 (see Alarm and RTC Programming section). When an alarm occurs in any mode, the ALIRQ bit of the AL_Status register will change from 0 to 1, and the INT output will go low unless you are in Sleep mode. If not already awake, the device will wake-up from Sleep mode to Standby mode and INT goes low when the PLL output is available. The crystal oscillator, RTC, wake-up circuitry, reset voltage monitor, low VDD voltage monitor (if applicable), and the PLL are all powered up in standby mode. Four alarm registers (Al_Sec, Al_Min, Al_Hour, and Al_Day) are used to store the preset time value for the alarm function. Bit 7 of the Al_Sec, Al_Min, Al_Hour, Al_Day registers is the mask bit and is used to program how often the alarm occurs. Table 7 shows how Bit 7 of the four alarm registers should be set for the time of day alarm to occur. Other combinations of mask bits are possible to set different alarms.
Table 6. BCD Conversion
DECIMAL DIGIT 0 1 2 3 4 5 6 7 8 9 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 UNUSED CODES 1010 1011 1100 1101 1110 1111
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Table 7. Common Mask Bits Combinations
ALARM REGISTER MASK BITS (BIT 7) AL_SEC 1 0 0 0 0 AL_MIN 1 1 0 0 0 M_HOUR 1 1 1 0 0 M_DAY 1 1 1 1 0 FUNCTION Alarm occurs once per second Alarm occurs when seconds match Alarm occurs when minutes and seconds match Alarm occurs when hours, minutes, and seconds match Alarm occurs when day, hours, minutes, and seconds match HOW OFTEN? Once per second Once per minute Once per hour Once per day Once per week
AL_BURST REGISTER (01000) Writing to this register begins the alarm burst mode transfer. All the alarm clock registers are consecutively
read from or written to starting with Bit7 of the Al_Sec register followed by the Al_Min register, Al_Hour register, and finally the Al_Day register.
AL_SEC REGISTER (01001)
FIRST BIT (MSB) NAME DEFAULT M_SEC 0 10SEC2 0 10SEC1 0 10SEC0 0 SEC3 0 SEC2 0 SEC1 0 (LSB) SEC0 0
M_SEC: Alarm mask bit. A logic 1 masks out the seconds alarm comparator. 10SEC[2:0]: These are the 10-second bits (0-50 seconds) of the alarm.
SEC[3:0]: These are the second bits (0-9 seconds) of the alarm.
AL_MIN REGISTER (01010)
FIRST BIT (MSB) NAME DEFAULT M_MIN 0 10MIN2 0 10MIN1 0 10MIN0 0 MIN3 0 MIN2 0 MIN1 0 (LSB) MIN0 0
M_MIN: Alarm mask bit. A logic 1 masks out the minute alarm comparator. 10MIN[2:0]: These are the 10-minute bits (0-50 minutes) of the alarm.
MIN[3:0]: These are the minute bits (0-9 minutes) of the alarm.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
AL_HOUR REGISTER (01011)
FIRST BIT (MSB) NAME DEFAULT M_HR 0 12/24 0 AP 0 10HR 0 HR3 0 HR2 0 HR1 0 (LSB) HR0 0
MAX1407/MAX1408/MAX1409/MAX1414
M_HR: Alarm mask bit. A logic 1 masks out the hour alarm comparator. 12/24: 12/24-hour mode bit. A logic 1 selects 12-hour mode while a logic 0 selects 24-hour mode. This bit must be the same as the 12/24-bit of the RTC_Hour register for correct operation.
AP: AM/PM bit. In 12-hour mode, a logic 1 indicates PM and a logic 0 indicates AM. In 24-hour mode, this bit is the second 10-hour bit (20 hours). 10HR: This is the 10-hour bit (0-10 hours) of the alarm. HR[3:0]: These are the hour bits (0-9 hours) of the alarm.
AL_DAY REGISTER (01100)
FIRST BIT (MSB) NAME DEFAULT M_DAY 0 -- 0 -- 0 -- 0 -- 0 DAY2 0 DAY1 0 (LSB) DAY0 1
M_DAY: Alarm mask bit. A logic 1 masks out the day alarm comparator.
DAY[2:0]: These are the day of the week bits (Sunday -Saturday). The following table is the Hex code for each day of the week.
AL_DAY DAY[2:0]
SUN 1h
MON 2h
TUE 3h
WED 4h
THU 5h
FRI 6h
SAT 7h
AL_STATUS REGISTER (01101)
FIRST BIT (MSB) NAME DEFAULT ALIRQ 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 (LSB) -- 0
ALIRQ: Alarm Interrupt Request Bit. A logic 1 indicates that the current time has matched the preset time in the alarm registers (this corresponds to the assertion of the
INT pin). ALIRQ resets to 0 when any alarm register is read or written to.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
ALARM/CLOCK_CTRL REGISTER (01110)
FIRST BIT (MSB) NAME DEFAULT WE 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 (LSB) AE 0
WE: Write Enable bit. WE must be set to "1" before any write operation to the clock and the alarm register. A logic 0 disables write operations to the clock and alarm registers, including the AE bit. The WE signal takes effect after the 8th SCLK rising edge for an 8-bit write. AE: Alarm Enable bit. A logic 0 disables the alarm function. When AE equals "1", the ALIRQ bit in the Al_Status register will be set to 1 whenever the current time matches that of the alarm registers. Real-Time Clock (RTC) The RTC_Sec, RTC_Min, RTC_Hour, RTC_Date, RTC_Month, RTC_Day, RTC_Year, and RTC_Century registers can be accessed one register at a time or in Burst mode (see RTC_BURST REGISTER section). The RTC runs continuously and does not stop for read or write operations. To prevent the data from changing during a read operation, complete all read operations on the RTC registers (single register reads and burst reads) in less than 1ms. Using single reads to read all the RTC registers could lead to errors as much as a century. Since the registers are updated between read operations, the register contents may change before all RTC registers have been read, when reading one register at a time. The most accurate way to get the time information of the RTC registers is with a burst read. In the burst read, a snapshot of the eight RTC registers (RTC_Sec, RTC_Min, RTC_Hour, RTC_Date, RTC_Month, RTC_Day, RTC_Year, RTC_Century) is taken once and read
sequentially with the MSB of the Seconds register first. They must all be read out as a group of eight registers of eight bits each, for proper execution of the burst read function. The worst-case error that can occur between the "actual" time and the "reported" time is one second. As with a read operation, using single writes to update the RTC can lead to collisions. To guarantee an accurate update of the RTC, use the Burst Write mode (see Alarm and RTC Programming section). The RTC defaults to 24-hr mode, 00:00:00, Sunday, January 01, 1970 during power-up. January 01, 1970 falls on a Thursday, but since this RTC is not timebased, the default values do not have an impact on the functionality of the clock, and they merely provide some means for testing. If the alarm or RTC registers are programmed to some unused states, the device chooses the default values. RTC_BURST REGISTER (01111) Writing to this address begins the burst mode transfer. In this mode, all the real-time clock registers are continuously read or written starting with Bit 7 of the RTC_Sec, RTC_Min, RTC_Hour, RTC_Date, RTC_Month, RTC_Day, RTC_Year, and RTC_Century registers. When reading, the contents of DIN will be ignored and each register's 8-bit data will be clocked out at DOUT on the falling edge of SCLK (total of 64 clock cycles). When writing, start with the Seconds' register MSB first and continue through the Century register (see Alarm and RTC Programming section). RTC_SEC REGISTER (10000)
FIRST BIT (MSB) NAME DEFAULT CH 0 10SEC2 0 10SEC1 0 10SEC0 0 SEC3 0 SEC2 0 SEC1 0
(LSB) SEC0 0
CH: Clock Halt bit. Writing a "1" to CH disables the real-time clock and oscillator. 10SEC[2:0]: These are the 10 second bits (10-50 seconds) of the RTC.
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SEC[3:0]: These are the second bits (0-9 seconds) of the RTC.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
RTC_MIN REGISTER (10001)
FIRST BIT (MSB) NAME DEFAULT -- 0 10MIN2 0 10MIN1 0 10MIN0 0 MIN3 0 MIN2 0 MIN1 0 (LSB) MIN0 0
MAX1407/MAX1408/MAX1409/MAX1414
10MIN[2:0]: These are the 10 minute bits (0-50 minutes) of the RTC.
MIN[3:0]: These are the minute bits (0-9 minutes) of the RTC. RTC_HOUR REGISTER (10010)
FIRST BIT (MSB) NAME DEFAULT -- 0 12/24 0 AP 0 10HR 0 HR3 0 HR2 0 HR1 0
(LSB) HR0 0
12/24: 12/24-hour mode bit. A logic 1 selects 12-hour mode while a logic 0 selects 24-hour mode. This bit must be the same as the 12-/24-bit of the AL_Hour register for correct operation.
AP: AM/PM-bit. In 12-hour mode, a logic 1 indicates PM and a logic 0 indicates AM. In 24 hour mode, this bit is the second 10-hour bit (20 hours). 10HR: This is the 10-hour bit (0-10 hours) of the RTC. HR[3:0]: These are the hour bits (0-9 hours) of the RTC.
RTC_DATE REGISTER (10011)
FIRST BIT (MSB) NAME DEFAULT -- 0 -- 0 10DATE1 0 10DATE0 0 DATE3 0 DATE2 0 DATE1 0 (LSB) DATE0 1
10DATE[1:0]: These are the 10 day bits (0-30 days) of the RTC.
DATE[3:0]: These are the day bits (0-9 days) of the RTC.
RTC_MONTH REGISTER (10100)
FIRST BIT (MSB) NAME DEFAULT -- 0 -- 0 -- 0 10MO 0 MO3 0 MO2 0 MO1 0 (LSB) MO0 1
10MO: This is the 10 month bit (0-10 months) of the RTC.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
10MO: This is the 10 month bit (10-12 months) MO[3:0]: These are the month bits (0-9 months) for the RTC. The following table is the Hex code for the twelve months of the year.
MAR 03h SEP 09h APR 04h OCT 10h MAY 05h NOV 11h JUN 06h DEC 12h
MONTH 10MO MO[3:0] MONTH 10MO MO[3:0]
JAN 01h JUL 07h
FEB 02h AUG 08h
RTC_DAY REGISTER (10101)
FIRST BIT (MSB) NAME DEFAULT -- 0 -- 0 -- 0 -- 0 -- 0 DAY2 0 DAY1 0 (LSB) DAY0 1
DAY[2:0]: These bits select the day of the week (Sunday-Saturday). The following table is the Hex code for day of the week.
AL_DAY DAY[2:0] SUN 1h MON 2h TUE 3h WED 4h THU 5h FRI 6h SAT 7h
RTC_YEAR REGISTER (10110)
FIRST BIT (MSB) NAME DEFAULT 10YEAR3 0 10YEAR2 1 10YEAR1 1 10YEAR0 1 YEAR3 0 YEAR2 0 YEAR1 0 (LSB) YEAR0 0
10YEAR[3:0]: These are the 10 year bits (0-90 years) of the RTC.
YEAR[3:0]: These are the year bits (0-9 years) of the RTC.
RTC_CENTURY REGISTER (10111)
FIRST BIT (MSB) NAME DEFAULT MILL3 0 MILL2 0 MILL1 0 MILL0 1 CENT3 1 CENT2 0 CENT1 0 (LSB) CENT0 1
MILL[3:0]: These are the millennium bits (0000-9000 years) of the RTC.
CENT[3:0]: These are the century bits (000-900 years) of the RTC.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Table 8. Related Bit Values During Specified Mode
CIRCUIT BLOCK 32kHz Oscillator RTC Low VDD Voltage Monitor (2.7V) RESET Voltage Monitor (1.8V) Reset Bit Low VDD Status Bit Voltage-Monitor Threshold Selection Bias Circuit PLL PLL Output SHDN Output DAC1 DAC2 ADC MUX Bandgap Reference Signal-Detect Comparator ADC Buffers ADC BIT CH CH LVDE LSDE RST LVD VM BIASE PLLE PLLE SHDE DA1E DA2E MUX REFE SDCE BUFE ADC INITIAL POWER-UP 0 (oscillator is on) 0 (RTC is on) 1 (2.7V monitor is on) 0 (1.8V monitor is off) 1 (RESET asserted) 1 (low VDD) 0 (select 2.7V) Biase = 1 (biase circuit is on) 1 (PLL is on) 1 (FOUT is enabled) 1 (SHDN pin = high) 0 0 0 0 0 0 0 SLEEP N/A N/A 1 if VM = 0 0 if VM = 1 0 if VM = 0 1 if VM = 1 N/A N/A N/A 0 0 0 0 0 0 0 0 0 0 0 STANDBY N/A N/A 1 0 if VM = 0 1 if VM = 1 N/A N/A N/A 1 1 1 1 0 0 0 0 0 0 0 IDLE N/A N/A 1 0 if VM = 0 1 if VM = 1 N/A N/A N/A 1 1 1 1 1 1 1 1 1 0 0 RUN N/A N/A 1 0 if VM = 0 1 if VM = 1 N/A N/A N/A 1 1 1 1 1 1 1 1 1 1 1 WAKE-UP EVENT N/A N/A 1 N/A N/A N/A N/A 1 1 1 1 N/A N/A N/A N/A N/A N/A N/A
N/A: Programming the part into these modes would not alter the content of the corresponding bit.
Power-Control Registers Table 8 shows the bit values of some key registers in different power modes under various conditions. Use
this as a quick reference when programming the MAX1407/MAX1408/MAX1409/MAX1414 family.
POWER1 REGISTER (11000)
FIRST BIT (MSB) NAME DEFAULT REFE 0 ADCE 0 BUFE 0 MUXE 0 DA1E 0 DA2E 0 -- 0 (LSB) -- 0
REFE: Internal Reference Power Enable. When REFE is set to 1, the internal reference is powered up. When REFE is set to 0, the internal reference is powered down allowing an external reference to be connected to REF. ADCE: ADC Power Enable. When ADCE is set to 1, the ADC is powered up. When ADCE is set to 0, the ADC is powered down.
BUFE: ADC Input Buffer Power Enable. A logic 1 enables the power-up of the ADC input buffers, while a logic 0 powers-down the buffers. MUXE: Multiplexer enable. A logic 0 disables the multiplexer outputs while a logic 1 enables them.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
DA1E: DAC1 Power Enable. A logic 1 powers DAC1, while a logic 0 powers it down. The output buffer goes high impedance in power-down mode. DA2E: DAC2 Power Enable. A logic 1 powers DAC2, while a logic 0 powers it down. The output buffer goes high impedance in power-down mode. POWER2 REGISTER (11001)
FIRST BIT (MSB) NAME DEFAULT SHDE 1 PLLE 1 LVDE 1 LSDE 0 SDCE 0 D0E 0 VM 0 (LSB) BIASE 1
SHDE: Shutdown Enable bar. If SHDE is set to 1, SHDN is pulled high. A wake-up event such as an assertion of WU1 or WU2, a time-of-day alarm, or by writing to the Power1, Power2, Standby, Idle, or Run registers sets this bit to 1 and drives SHDN high. If the SHDE bit is set to 0 in Standby, Idle, or Run mode and the PLL is still operational (PLLE = 1), the SHDN pin will remain high until 2.93ms (tDPD) after PLLE is set to 0. PLLE: Phase-Locked Loop Power Enable. A logic 1 powers the PLL and enables FOUT while a logic 0 powers down the PLL and disables FOUT. A wake-up event sets this bit to 1. See Wake-Up section. LVDE: +2.7V Voltage Monitor Power Enable. A logic 1 powers the +2.7V voltage comparator circuitry, while a logic 0 powers down the +2.7V voltage comparator circuitry. A wake-up event sets LVDE to 1. See Wake-Up section. LSDE: +1.8V Voltage Monitor Power Enable. A logic 1 powers the +1.8V voltage comparator circuitry, while a logic 0 powers down the +1.8V voltage comparator circuitry. See Wake-Up section. SDCE: Signal-Detect Comparator Power Enable. A logic 1 powers the signal-detect comparator while a logic 0 powers down this comparator. D0E: D0 Enable bit. A logic 0 three-states the D0 ouput. When D0E is set to "1", the output of D0 is contolled by the state of DBIT in the MUX register. Programming the device in different modes does not alter the state of this bit. VM: RESET Voltage Monitor Threshold Selection bit. A logic 0 selects a +2.7V threshold while a logic 1 selects a +1.8V threshold for the RESET Voltage Monitor. The VM bit effects the LVDE and LSDE bits in different modes of operation (see Table 8). BIASE: Bias Enable. A logic 1 powers up the master bias circuit block. A wake-up event sets this bit to a logic 1. See Wake-Up section.
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SLEEP REGISTER (11010) Addressing the Sleep register places the MAX1407/ MAX1408/MAX1409/MAX1414 in Sleep mode. This occurs after the last bit of the command byte is clocked into the device. It requires an 8-bit write, no data bits are needed. Sleep mode powers down all functional blocks except for the crystal oscillator, RTC, alarm, serial interface, wake-up circuitry, and RESET voltage monitor. While in Sleep mode, pulling either WU1 or WU2 low or an alarm event places the device into Standby mode. STANDBY REGISTER (11011) Addressing the Standby register places the MAX1407/ MAX1408/MAX1409/MAX1414 in Standby mode. This occurs after the last bit of the address byte is clocked into the device. It requires an 8-bit write, no data bits are needed. Standby mode powers up the same blocks as Sleep mode, as well as the master bias circuitry, the PLL, and the Low VDD Voltage Monitor. FOUT is also enabled and SHDN is set high in Standby mode. IDLE REGISTER (11100) Addressing the Idle register places the MAX1407/ MAX1408/MAX1409/MAX1414 in Idle mode. This occurs after the last bit of the address byte is clocked into the device. Requires an 8-bit write, no data bits are needed. In Idle mode, all circuits are powered up with the exception of the ADC and the ADC Input Buffers. RUN REGISTER (11101) Addressing the Run register puts the MAX1407/ MAX1408/MAX1409/MAX1414 into Run mode. This occurs after the last bit of the address byte is clocked into the device. Requires an 8-bit write, no data bits are needed. All the functional blocks are powered up in Run mode.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
Applications Information
Alarm and RTC Programming
Three write operations are needed for every update of the ALARM and RTC registers. First set the WE bit of the Alarm/Clock_CTRL Register to 1. Update the Alarm, RTC, and Alarm/Clock_CTRL Register with the new values, and then set the WE bit back to 0. This will avoid collisions in setting the time. Idle Mode In Idle mode, only the ADC and ADC input buffers are shutdown. All the other blocks are powered up. Enter Idle mode by addressing the Idle register. Run Mode In Run mode, all the functional blocks are powered up and the ADC is ready to start conversion. Enter Run mode by either writing to the Run register or by individually powering up each circuit through the serial interface.
MAX1407/MAX1408/MAX1409/MAX1414
Power-On Reset or Power-Up
At initial power-up, the MAX1407/MAX1408/MAX1409/ MAX1414 are in Standby mode. Figure 15 illustrates the timing of various signals during initial Power-Up, Sleep mode, and Wake-Up. tDSLP after AVDD exceeds +2.7V, RESET goes high. tDFON after RESET goes high, FOUT is enabled. INT is enabled to t DFI after FOUT is enabled.
Wake-Up
Wake-Up mode is entered whenever a wake-up event, such as an assertion of WU1 or WU2 or a time-of-day alarm occurs. The Low VDD monitor, PLL, FOUT are enabled, and SHDN goes high. Different from the Standby mode, the status of the other power blocks remains unchanged.
Power Modes
The MAX1407/MAX1408/MAX1409/MAX1414 have fou distinct power modes, Sleep mode, Standby mode, Idle mode, and Run mode. Table 9 lists the power-on status of the various blocks of the MAX1407/MAX1408/ MAX1409/MAX1414. Each individual circuit block can be powered up through the serial interface by writing to the appropriate power registers. Sleep Mode In Sleep mode, only the crystal oscillator, RTC, data registers, wake-up circuitry, and RESET Voltage Monitor are powered up. Sleep mode is entered by addressing the Sleep register through the serial interface. Sleep mode preserves any data in the data registers. To exit Sleep mode, pull either WU1 or WU2 low or address other Power mode registers (Standby, Idle, Run, Power1, or Power2 registers). Asserting WU1 or WU2 or the occurence of a Time of Day Alarm while in Sleep mode places the device in Standby mode. Standby Mode After initial power-up or after exiting Sleep mode through a wake-up event, the MAX1407/MAX1408/ MAX1409/MAX1414 are in Standby mode. Standby mode can also be entered by addressing the Standby register. In Standby mode, SHDN is high, FOUT is enabled, the Low VDD voltage monitor and the PLL are powered up, and INT is low. INT will return to a logic high after the P begins writing to any register through the serial interface (once a start bit is detected through the serial interface).
Analog Filtering
The digital filter does not provide any rejection close to the harmonics of the modulator sample frequency. However, due to the high oversampling ratio of the MAX1407/MAX1408/MAX1409/MAX1414, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. Therefore, the analog filtering requirements in front of the MAX1407/MAX1408/ MAX1409/MAX1414 are considerably reduced compared to a conventional converter with no on-chip filtering. In addition, because the part's common-mode rejection of 90dB extends out to several kHz, commonmode noise susceptibility in this frequency range is substantially reduced. Depending on the application, it may be necessary to provide filtering prior to the MAX1407/MAX1408/ MAX1409/MAX1414 to eliminate unwanted frequencies the digital filter does not reject. It may also be necessary in some applications to provide additional filtering to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator. If passive components are placed in front of the MAX1407/MAX1408/MAX1409/MAX1414 when the part is used in unbuffered mode, ensure that the source impedance is low enough not to introduce gain errors in the system. This can significantly limit the amount of passive anti-aliasing filtering that can be applied in front of the MAX1407/MAX1408/MAX1409/MAX1414 in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small DC offset error (a 1k source resistance will cause an offset error of less than 0.5V). Therefore, where significant source impedances are required, operate the device in buffered mode.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
4 3 2.7V 2 1 0v HI tDSLP LO HI 32kHz CLOCK LO HI WU1,WU2 (INT. PULLUP) tWU LO tDPU HI SHDN LO tDFON FOUT (2.4576MHz) HI LO tDFI HI INT LO HI DRDY LO HI DOUT LO HI CS LO HI LO SLEEP WRITE THREE-STATED tDFOF tDFI tDPD tDFON AVDD
RESET (OPEN-DRAIN)
SCLK, DIN
INITIAL POWER-UP
SLEEP MODE
WAKE-UP
Figure 15. Initial Power-up, Sleep Mode, and Wake-Up Timing Diagram with AVDD >2.7V
Dynamic Input Impedance
When designing with the MAX1407/MAX1408/ MAX1409/MAX1414, as with any other switched-capacitor ADC input, consider the advantages and disadvan38
tages of series input resistance. A series resistor reduces the transient current impulse to the external driving amplifier. This improves the amplifier phase margin and reduces the possibility of ringing. The resis-
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Table 9. Power States of Individual Blocks at Different Modes of Operation
CIRCUIT BLOCKS Serial Interface Wake-Up Circuitry Crystal Oscillator RTC with Alarm RESET Voltage Monitor Low VDD Voltage Monitor Master Bias Circuit PLL FOUT SHDN = High DAC1 DAC2 Bandgap Bandgap Buffer Signal Detect Comparator ADC Multiplexer ADC Input Buffers ADC POWER MODES SLEEP x x x x x -- -- -- -- -- -- -- -- -- -- -- -- -- STANDBY x x x x x x x x x x -- -- -- -- -- -- -- -- IDLE x x x x x x x x x x x x x x x x -- -- RUN x x x x x x x x x x x x x x x x x x WAKE-UP EVENT x x x x x x x x x x N/A N/A N/A N/A N/A N/A N/A N/A
x = powered-up N/A = programming the parts into the wake-up mode would not alter the content of these blocks
Table 10. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered Mode
PGA GAIN (V/V) 1 2 EXTERNAL RESISTANCE REXT (k) CEXT = 0pF 194 100 CEXT = 50pF 56 30 CEXT = 100pF 33 16 CEXT = 200pF 19 9 CEXT = 500pF 9 4.5
tor spreads the transient-load current from the sampler over time due to the RC time constant of the circuit. However, an improperly chosen series resistance can hinder performance in high-resolution converters. The settling time of the RC network can limit the speed at which the converter can operate properly, or reduce the settling accuracy of the sampler. In practice, this means ensuring that the RC time constant, resulting from the product of the driving source impedance and the capacitance presented by both the device's input and any external capacitance is sufficiently small to allow settling to the desired accuracy. Table 10 summarizes the maximum allowable series resistance vs.
external shunt capacitance for each different gain setting in order to ensure 16-bit performance in unbuffered mode (for 60sps conversion rate).
Performing a Conversion or OffsetCalibration with the ADC
Upon power-up, the MAX1407/MAX1408/MAX1409/ MAX1414 are in Standby mode. At this point, the ADC register default settings are set for a normal ADC conversion (MODE = 0), conversion rate of 30Hz (RATE = 0), gain of 1/3 V/V (GAIN [00]), input buffers bypassed and powered down (BUFP = BUFN = 0), and unipolar mode
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
R1 REF
MAX1407/MAX1409/MAX1414 FB1
R2
FB_
OUT1
+5V VOUT
DAC 1 REF FB2
DAC_ OUT_ -5V R2 = R1
MAX1407/MAX1409/MAX1414
DAC 2 AGND DGND OUT2
Figure 18. Bipolar Output Circuit
THE MAX1409 HAS ONE DAC VREF = 1.25V
will keep doing conversions at a rate of 30Hz until powered down. To perform an on-chip offset calibration on a specific configuration, write to the ADC register with the MODE bit and STA1 bit set to 1. The ADC will do one calibration using the inputs to the ADC specified in the MUX register and then stop. The calibration result will be stored in the Offset register in two's complement form. Subsequent ADC conversion results will have the offset value subtracted before written to the DATA register. The MODE bit will be reset to 0 automatically upon completion of the calibration. The ADC is now ready for a normal conversion.
OUT1 FB2 10k
Figure 16. Unipolar Output Circuit
MAX1407/MAX1409/MAX1414
FB1
10k
10k DAC 1 REF 10k DAC 2 AGND DGND OUT2
The offset for a given ADC configuration can be stored by the P to avoid another ADC recalibration. Write the stored offset back to the offset register when returning back to that particular ADC configuration where the calibration was taken. Subsequent ADC conversion results will have the offset value subtracted before they are written to the DATA register.
DAC Unipolar Output
For a unipolar output, the output voltages and the reference have the same polarity. Figure 16 shows the MAX1407/MAX1409/MAX1414s' unipolar output circuit, which is also the typical operating circuit for the DACs. Table 11 lists some unipolar input codes and their corresponding output voltages. For larger output swing see Figure 17. This circuit shows the output amplifiers configured with a closedloop gain of +2V/V to provide 0 to 2.5V full-scale range with the 1.25V reference.
THE MAX1409 HAS ONE DAC VREF = 1.25V
Figure 17. Unipolar Rail-to-Rail Output Circuit
(BIP = 0). To initiate an ADC conversion: 1) Enter Run mode by addressing the Run register 2) Select the desired channels for conversion by writing to the MUX register, (e.g., 94h selects IN1 for the positive channel and IN2 for the negative channel) 3) Initiate the conversion by writing to the ADC register, (e.g., 01h). The first conversion result becomes available in 100ms. The ADC
DAC Bipolar Output
The MAX1407/MAX1409/MAX1414 DAC outputs can be configured for bipolar operation using the application circuit on Figure 18:
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Table 11. Unipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 11 1000 0000 01 1000 0000 00 0111 1111 11 0000 0000 01 0000 0000 00 ANALOG OUTPUT +VREF(1023/1024) +VREF (513/1024) +VREF (512/1024) = +VREF/2 +VREF (511/1024) +VREF (1/1024) 0
Table 12. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 11 1000 0000 01 1000 0000 00 0111 1111 11 0000 0000 01 0000 0000 00 ANALOG OUTPUT +VREF (511/512) +VREF (1/512) 0 -VREF (1/512) -VREF (511/512) -VREF (512/512) = -VREF
LX 10H
OUT RST
VDD = 3.3V OR VBAT
10F MAX1833 BATT GND SHDN
18nF
0.1F
0.1F
0.1F
CPLL SHDN IN0
AVDD MAX1407 MAX1408 MAX1414
DVDD RESET RESET
VDD
P/C WU1 DGND INPUT VSS
VBAT
E1*
10F AGND
*ONE Li+ COIN, TWO ALKALINE, OR TWO BUTTON CELLS
Figure 19. Power-Supply Circuit Using MAX1833 Step-Up DC-DC Converter
0.33F
IN
CXN
CXP
OUT POK
VDD = 3.3V
10F MAX1759 SHDN GND PGND
18nF
0.1F
0.1F
0.1F
FB
CPLL SHDN
AVDD MAX1407 MAX1408 MAX1414
DVDD RESET RESET
VDD
R IN0 VBAT E1* 10F R AGND
P/C WU1 DGND INPUT VSS
*ONE Li+ COIN, ONE Li+, 2-3 ALKALINE, 2-3 NIMH, OR 2-3 BUTTON CELLS
Figure 20. Power-Supply Circuit Using MAX1759 Buck-Boost DC-DC Converter ______________________________________________________________________________________ 41
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
100H V+ SHDN MAX640 LX D1 100F 18nF VOUT LBI VFB GND CPLL AVDD MAX1407 MAX1408 MAX1409 MAX1414 AGND DGND DVDD RESET 2R IN0 VBAT R 33F VSS WU1 RESET P/C INPUT VDD 0.1F 0.1F 0.1F VDD (+3.3V)
E1*
*ONE TRANSISTOR (9V), ONE J CELL (6V), OR FOUR ALKALINE CELLS
Figure 21. Power-Supply Circuit Using MAX640 Step-Down DC-DC Converter
VBAT
E1*
10F 18nF
0.1F 0.1F 0.1F
CPLL
AVDD MAX1407 MAX1408 MAX1409 MAX1414
DVDD RESET WU1
VDD RESET P/C INPUT
20, 21, and 22 are power-supply circuits using a step-up converter, buck-boost converter, step-down converter, and a direct battery, respectively. Choose the correct power-supply circuit for your specific application. Connect the MAX1407/MAX1408/MAX1409/MAX1414 AVDD and DVDD power supplies together. While the latch-up performance of the MAX1407/MAX1408/ MAX1409/MAX1414 is adequate, it is important that power is applied to the device before the analog input signals (IN_) to avoid latch-up. If this is not possible, limit the current flow into any of these pins to 50mA.
AGND
DGND
VSS
Electrochemical Sensor Operation
The MAX1407/MAX1408/MAX1409/MAX1414 family interface with electrochemical sensors. The 10-bit DACs with the force/sense buffers have the flexibility to connect to many different types of sensors. Figure 23 shows how to interface with a two electrode potentiostat. A single DAC is required to set the bias across the sensor relative to ground and an external precision resistor completes the transimpedance amplifier configuration to convert the current generated by the sensor to a voltage to be measured by the ADC. The induced error from this source is negligible due to FB1's extremely low input bias current. Internally, the ADC can differentially measure directly across the external transimpedance resistor, RF, eliminating any errors due to voltages drifting over time, temperature, or supply voltage. Figure 24 shows a two electrode potentiostat application that is driven at the working electrode and measured at the counter electrode. With this application, the DAC connected to the working electrode is configured in unity gain and the DAC connected to the
*ONE Li+ COIN OR TWO BUTTON CELLS
Figure 22. Power-Supply Circuit Using Direct Battery Connection
2NB VOUT = VREF - 1 1024 where NB is the decimal value of the DAC's binary input code. Table 12 shows digital codes (offset binary) and corresponding output voltages for Figure 18 assuming R1 = R2.
Power Supplies
Power to the MAX1407/MAX1408/MAX1409/MAX1414 family can be supplied in a number of ways. Figures 19,
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
MAX1407 MAX1409 MAX1414 REF 10-BIT DAC OUT1 IF FB1 AUX. VOLTAGE INPUTS IN0 IN1 IN2 IN3 WE SENSOR CE RF AUX. VOLTAGE INPUTS IN0 IN1 IN2 IN3 REF 10-BIT DAC OUT2 FB2 BAND GAP BUF REF 4.7F BAND GAP REF 4.7F IF FB1 WE SENSOR CE RF
MAX1407 MAX1414 REF 10-BIT DAC OUT1
BUF
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR. MAX1409 HAS IN0, OUT1, FB1, AND REF ONLY.
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
Figure 23. Self-Biased Two Electrode Potentiostat Application
Figure 24. Driven Two Electrode Potentiostat Application
MAX1407 MAX1414 REF 10-BIT DAC IN0 IN1 IN2 IN3 REF 10-BIT DAC OUT2 OUT1 IF FB1 FB2 WE RE CE SENSOR RF
MAX1407 MAX1414 REF 10-BIT DAC OUT1
VBAT LED
QB FB1 RB REF 10-BIT DAC OUT2 IF FB2 BAND GAP BUF REF 4.7F AUX. VOLTAGE INPUTS IN0 IN1 IN2 IN3 BAND GAP REF 4.7F PHOTODIODE RF AUX. VOLTAGE INPUTS
BUF
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
ALL I/O AVAILABLE AS INPUTS TO ADC AND COMPARATOR.
Figure 25. Driven Three Electrode Potentiostat Application
Figure 26. Optical Reflectometry Application
counter electrode is configured as a transimpedance amplifier to measure the current. Figure 25 shows a three electrode potentiostat application that is driven at all the electrodes and measured at the working electrode. With this application, the DAC connected to the working elec-
trode sets the bias voltage relative to the reference electrode and also measures the current that the sensor produces. The DAC connected to the reference and counter electrodes takes advantage of the force/sense outputs to
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
REF RL IN0 8:1 MUX
REF 16b ADC DRDY CMP WAKE-UP MAX1407 MAX1408 MAX1409 MAX1414 DRDY NOT AVAILABLE ON THE MAX1409 BAND GAP INTERRUPT GENERATOR INT
RT 8:1 MUX
AGND
BUF
REF 4.7F
Figure 27. Thermistor Application Circuit
CJC THERMOCOUPLE JUNCTION IN0 R C IN1 8:1 MUX
REF 16b ADC DRDY CMP WAKE-UP BAND GAP INTERRUPT GENERATOR INT
R C
AGND IN2 REF 4.7F
8:1 MUX
BUF
MAX1407 MAX1408 MAX1414
Figure 28. Thermocouple Application Circuit
maintain the reference electrode bias voltage by virtue of the feedback path through the sensor.
photodiode. Set the LED bias current externally if the MAX1409 is used in this application.
Optical Reflectometry
Figure 26 illustrates the MAX1407/MAX1414 in an optical reflectometry application. The first DAC is used with an external transistor to set the bias current through the LED and the second DAC is used to properly bias and convert the photodiode current to a voltage measured by the ADC. The low input bias current into the DAC feedback pin (FB2) allows the measurement of very small currents. The DACs provide the flexibility in setting an accurate and stable LED current and adjusting the bias across the
Thermistor Measurement
A thermistor connected in a half-bridge configuration as shown in Figure 27 is used to measure temperatures very accurately with the MAX1407/MAX1408/ MAX1409/MAX1414. The internal reference drives the thermistor as well as the ADC, so the reference variation is cancelled out when calculating the temperature. The only significant errors are from the RL resistor and the thermistor itself. The ADC performs a unipolar conversion with the PGA set to a gain of 1V/V.
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
REF OR AVDD REF RA RB IN0 8:1 MUX 16-BIT ADC DRDY RD RC IN1 CMP WAKE-UP MAX1407 MAX1408 MAX1414 DRDY NOT AVAILABLE ON THE MAX1409 BAND GAP INTERRUPT GENERATOR INT
8:1 MUX
BUF
REF 4.7F
Figure 29. Strain-Gauge Application Circuit
Thermocouple Measurement
Figure 28 shows a thermocouple connected to the differential inputs of the MAX1407/MAX1408/MAX1409/ MAX1414. In this application, the internal buffers are enabled to allow for the decoupling shown at the input. The decoupling eliminates noise pickup from the thermocouple. With the internal buffers enabled, the input common-mode range is reduced so the IN2 input is biased to the internal reference voltage at +1.25V. When the buffer is enabled, the IN1 input is limited to +1.4V.
Strain-Gauge Operation
Connect the differential inputs of the MAX1407/ MAX1408/MAX1409/MAX1414 to the bridge network of the strain gauge as shown in Figure 29. When connected to the internal reference, the ADC can resolve below 10V at the differential inputs. The internal buffers provide a high input impedance as long as the signal is within the reduced common-mode range of the input buffers. The bridge may also be driven directly from the supply voltage. In this configuration, the ADC first measures the supply voltage and then the differential input in sequence, and then calculates the ratio.
Grounding and Layout
For best performance, use printed circuit boards with separate analog and digital ground planes. The device perfomance will be highly degraded when using wirewrap boards. Design the printed circuit board so that the analog and digital sections are separated and confined to different areas of the board. Join the digital and analog ground planes at one point. If the MAX1407/MAX1408/ MAX1409/MAX1414 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND pin of the MAX1407/
MAX1408/MAX1409/MAX1414. In systems where multiple devices require AGND to DGND connections, the connection should still be made at only one point. Make the star ground as close to the MAX1407/MAX1408/ MAX1409/MAX1414 as possible. Avoid running digital lines under the device because these may couple noise onto the die. Run the analog ground plane under the MAX1407/MAX1408/ MAX1409/MAX1414 to minimize coupling of digital noise. Make the power-supply lines to the MAX1407/ MAX1408/MAX1409/MAX1414 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. Shield fast switching signals such as clocks with digital ground to avoid radiating noise to other sections of the board. Avoid running clock signals near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough on the board. A microstrip technique is best, but is not always possible with double-sided boards. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good coupling is important when using high-resolution ADCs. Decouple all analog supplies with 1F capacitors in parallel with 0.1F HF ceramic capacitors to AGND. Place these components as close to the device as possible to achieve the best decoupling.
Crystal Layout
Since it is possible for noise to be coupled onto the crystal pins, care must be taken when placing the external crystal on a PC board layout. It is very important to follow a few basic layout guidelines concerning
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
the placement of the crystal on the PC board layout to insure that extra clock "ticks" do not couple onto the crystal pins. 1) It is important to place the crystal as close as possible to the CLKIN and CLKOUT pins. Keeping the trace lengths between the crystal and pins as small as possible reduces the probability of noise coupling by reducing the length of the "antennae". Keeping the trace lengths small also decreases the amount of stray capacitance. 2) Keep the crystal bond pads and trace width to the CLKIN and CLKOUT pins as small as possible. The larger these bond pads and traces are, the more likely it is that noise can couple from adjacent signals. 3) If possible, place a guard ring (connect to ground) around the crystal. This helps to isolate the crystal from noise coupled from adjacent signals. 4) Insure that no signals on other PC board layers run directly below the crystal or below the traces to the CLKIN and CLKOUT pins. The more the crystal is isolated from other signals on the board, the less likely it is that noise will be coupled into the crystal. There should be a minimum of 0.200 inches between any digital signal and any trace connected to CLKIN or CLKOUT. 5) It may also be helpful to place a local ground plane on the PC board layer immediately below the crystal guard ring. This helps to isolate the crystal from noise coupling from signals on other PC board layers. Note: The ground plane needs to be in the vicinity of the crystal only and not on the entire board.
Definitions
Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function (with offset and gain error removed) from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1407/MAX1408/MAX1409/MAX1414 are measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Pin Configurations (continued)
TOP VIEW
IN7 1 DO 2 IN6 3 IN4 4 IN0 5 REF 6 AGND 7 AVDD 8 CPLL 9 WU1 10 WU2 11 RESET 12 IN1 13 IN2 14 28 IN5 27 IN3 26 DVDD 25 DGND 24 CS 23 SCLK FB1 1 OUT1 2 IN0 3 REF 4 AGND 5 AVDD 6 CPLL 7 WU1 WU2 8 9 20 DVDD 19 DGND 18 CS 17 SCLK
MAX1409
16 DIN 15 DOUT 14 INT 13 CLKIN 12 CLKOUT 11 FOUT
MAX1408
22 DIN 21 DOUT 20 INT 19 CLKIN 18 CLKOUT 17 FOUT 16 DRDY 15 SHDN
RESET 10
46
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Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC
Typical Operating Circuit
LX OUT RST DC-DC CONVERTER BATT GND SHDN CPLL SHDN IN0 REF VBAT CLKOUT IN1 FOUT CS SCLK DIN DOUT INT DRDY FB1 SENSOR WE RE CE WU1 FB2 WU2 I/O I/O CLKIN OUTPUT SCK MOSI MISO INPUT INPUT AVDD DVDD RESET CLKIN RESET P/C VDD
MAX1407/MAX1408/MAX1409/MAX1414
MAX1407 MAX1414 OUT1
OUT2 AGND DGND VSS
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47
Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC MAX1407/MAX1408/MAX1409/MAX1414
Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
48 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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